| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/WebAssembly/ |
| D | umulo-i64.ll | 2 ; Test that UMULO works correctly on 64-bit operands.
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 232 SMULO, UMULO, enumerator
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 238 SMULO, UMULO, enumerator
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 257 SMULO, UMULO, enumerator
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCCTRLoops.cpp | 336 case Intrinsic::umul_with_overflow: Opcode = ISD::UMULO; break; in mightUseCTR()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 233 case ISD::UMULO: return "umulo"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 137 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; in PromoteIntegerResult()
786 if (N->getOpcode() == ISD::UMULO) { in PromoteIntRes_XMULO()
1401 case ISD::UMULO: in ExpandIntegerResult()
2548 if (N->getOpcode() == ISD::UMULO) { in ExpandIntRes_XMULO()
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| D | SelectionDAG.cpp | 2129 case ISD::UMULO: in computeKnownBits()
2620 case ISD::UMULO: in ComputeNumSignBits()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 275 case ISD::UMULO: return "umulo"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 139 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; in PromoteIntegerResult()
822 if (N->getOpcode() == ISD::UMULO) { in PromoteIntRes_XMULO()
1476 case ISD::UMULO: in ExpandIntegerResult()
2709 if (N->getOpcode() == ISD::UMULO) { in ExpandIntRes_XMULO()
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| D | SelectionDAG.cpp | 2541 case ISD::UMULO: in computeKnownBits()
3357 case ISD::UMULO: in ComputeNumSignBits()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | LegalizeIntegerTypes.cpp | 119 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; in PromoteIntegerResult()
659 if (N->getOpcode() == ISD::UMULO) { in PromoteIntRes_XMULO()
1156 case ISD::UMULO: in ExpandIntegerResult()
2250 if (N->getOpcode() == ISD::UMULO) { in ExpandIntRes_XMULO()
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| D | SelectionDAG.cpp | 1738 case ISD::UMULO: in ComputeMaskedBits()
2173 case ISD::UMULO: in ComputeNumSignBits()
6023 case ISD::UMULO: return "umulo"; in getOperationName()
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| D | LegalizeDAG.cpp | 861 case ISD::UMULO: in LegalizeOp()
3598 case ISD::UMULO: in ExpandNode()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | xmulo.ll | 216 ; UMULO
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1707 setOperationAction(ISD::UMULO, MVT::i64, Custom); in SparcTargetLowering()
2961 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); in LowerUMULO_SMULO()
3081 case ISD::UMULO: in LowerOperation()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1719 setOperationAction(ISD::UMULO, MVT::i64, Custom); in SparcTargetLowering()
2995 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); in LowerUMULO_SMULO()
3115 case ISD::UMULO: in LowerOperation()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 617 setOperationAction(ISD::UMULO, VT, Expand); in initActions()
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| /external/llvm/test/CodeGen/X86/ |
| D | xaluo.ll | 344 ; UMULO
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 249 setOperationAction(ISD::UMULO, MVT::i32, Custom); in AArch64TargetLowering()
250 setOperationAction(ISD::UMULO, MVT::i64, Custom); in AArch64TargetLowering()
1645 case ISD::UMULO: { in getAArch64XALUOOp()
2347 case ISD::UMULO: in LowerOperation()
3639 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) { in LowerBR_CC()
4088 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) { in LowerSELECT()
|
| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 884 setOperationAction(ISD::UMULO, VT, Expand); in initActions()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 319 setOperationAction(ISD::UMULO, MVT::i32, Custom); in AArch64TargetLowering()
320 setOperationAction(ISD::UMULO, MVT::i64, Custom); in AArch64TargetLowering()
1939 case ISD::UMULO: { in getAArch64XALUOOp()
2036 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)); in isOverflowIntrOpRes()
2817 case ISD::UMULO: in LowerOperation()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 1589 setOperationAction(ISD::UMULO, VT, Custom); in X86TargetLowering()
15905 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && in LowerSELECT()
15917 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; in LowerSELECT()
15921 if (CondOpcode == ISD::UMULO) in LowerSELECT()
15929 if (CondOpcode == ISD::UMULO) in LowerSELECT()
16550 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { in LowerBRCOND()
16602 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && in LowerBRCOND()
16627 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; in LowerBRCOND()
16633 if (CondOpcode == ISD::UMULO) in LowerBRCOND()
16641 if (CondOpcode == ISD::UMULO) in LowerBRCOND()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 1659 setOperationAction(ISD::UMULO, VT, Custom); in X86TargetLowering()
19058 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && in LowerSELECT()
19070 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; in LowerSELECT()
19074 if (CondOpcode == ISD::UMULO) in LowerSELECT()
19082 if (CondOpcode == ISD::UMULO) in LowerSELECT()
19663 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { in LowerBRCOND()
19715 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && in LowerBRCOND()
19740 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; in LowerBRCOND()
19746 if (CondOpcode == ISD::UMULO) in LowerBRCOND()
19754 if (CondOpcode == ISD::UMULO) in LowerBRCOND()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 1123 setOperationAction(ISD::UMULO, VT, Custom); in X86TargetLowering()
1128 setOperationAction(ISD::UMULO, MVT::i8, Expand); in X86TargetLowering()
10091 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs in LowerXALUO()
10446 case ISD::UMULO: return LowerXALUO(Op, DAG); in LowerOperation()
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