| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 43 UXTX, enumerator
63 case AArch64_AM::UXTX: return "uxtx"; in getShiftExtendName()
130 case 3: return AArch64_AM::UXTX; in getExtendType()
157 case AArch64_AM::UXTX: return 3; break; in getExtendEncoding()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 43 UXTX, enumerator
63 case AArch64_AM::UXTX: return "uxtx"; in getShiftExtendName()
130 case 3: return AArch64_AM::UXTX; in getExtendType()
157 case AArch64_AM::UXTX: return 3; break; in getExtendEncoding()
|
| /external/vixl/src/aarch64/ |
| D | operands-aarch64.cc | 322 VIXL_ASSERT(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX))); in Operand()
342 (((extend_ == UXTX) || (extend_ == SXTX)) && (shift_amount_ == 0))); in IsPlainRegister()
368 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_); in ToExtendedRegister()
|
| D | disasm-aarch64.cc | 167 const char *form = ((mode == UXTX) || (mode == SXTX)) ? "'Rds, 'Rns, 'Xm'Ext" in VisitAddSubExtended()
170 ((mode == UXTX) || (mode == SXTX)) ? "'Rns, 'Xm'Ext" : "'Rns, 'Wm'Ext"; in VisitAddSubExtended()
5610 (instr->GetExtendMode() == UXTX))) { in SubstituteExtendField()
5649 if (!((ext == UXTX) && (shift == 0))) { in SubstituteLSRegOffsetField()
|
| D | macro-assembler-aarch64.cc | 899 ((operand.GetExtend() != UXTX) && (operand.GetExtend() != SXTX))); in LogicalMacro()
1859 ((operand.GetExtend() != UXTX) && (operand.GetExtend() != SXTX))); in AddSubWithCarryMacro()
|
| D | constants-aarch64.h | 294 UXTX = 3, enumerator
|
| D | simulator-aarch64.cc | 449 case UXTX: in ExtendValue()
1405 VIXL_ASSERT((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
|
| /external/vixl/test/aarch64/ |
| D | test-api-aarch64.cc | 337 VIXL_CHECK(Operand(x5, UXTX).IsPlainRegister()); in TEST()
349 VIXL_CHECK(!Operand(x5, UXTX, 1).IsPlainRegister()); in TEST()
|
| D | test-assembler-aarch64.cc | 804 __ Orr(x9, x0, Operand(x1, UXTX, 3)); in TEST()
898 __ Orn(x9, x0, Operand(x1, UXTX, 3)); in TEST()
965 __ And(x9, x0, Operand(x1, UXTX, 3)); in TEST()
1103 __ Bic(x9, x0, Operand(x1, UXTX, 3)); in TEST()
1227 __ Eor(x9, x0, Operand(x1, UXTX, 3)); in TEST()
1294 __ Eon(x9, x0, Operand(x1, UXTX, 3)); in TEST()
9363 __ Adc(x13, x1, Operand(x2, UXTX, 4)); in TEST()
9375 __ Adc(x23, x1, Operand(x2, UXTX, 4)); in TEST()
15222 __ adds(xzr, x0, Operand(x1, UXTX)); in TEST()
15223 __ adds(xzr, x1, Operand(xzr, UXTX)); in TEST()
[all …]
|
| D | test-disasm-aarch64.cc | 436 COMPARE(add(x12, x13, Operand(x14, UXTX, 4)), "add x12, x13, x14, uxtx #4"); in TEST()
448 COMPARE(cmn(sp, Operand(xzr, UXTX, 3)), "cmn sp, xzr, lsl #3"); in TEST()
462 COMPARE(sub(x12, x13, Operand(x14, UXTX, 4)), "sub x12, x13, x14, uxtx #4"); in TEST()
474 COMPARE(cmp(sp, Operand(xzr, UXTX, 3)), "cmp sp, xzr, lsl #3"); in TEST()
|
| /external/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 362 UXTX, enumerator
|
| /external/v8/src/arm64/ |
| D | assembler-arm64-inl.h | 294 DCHECK(reg.Is64Bits() || ((extend != SXTX) && (extend != UXTX)));
337 return Operand(reg_, reg_.Is64Bits() ? UXTX : UXTW, shift_amount_);
|
| D | disasm-arm64.cc | 145 const char *form = ((mode == UXTX) || (mode == SXTX)) ? in VisitAddSubExtended()
147 const char *form_cmp = ((mode == UXTX) || (mode == SXTX)) ? in VisitAddSubExtended()
3944 (instr->ExtendMode() == UXTX))) { in SubstituteExtendField()
3977 if (!((ext == UXTX) && (shift == 0))) { in SubstituteLSRegOffsetField()
|
| D | macro-assembler-arm64.cc | 208 ((operand.extend() != UXTX) && (operand.extend() != SXTX))); in LogicalMacro()
788 ((operand.extend() != UXTX) && (operand.extend() != SXTX))); in AddSubWithCarryMacro()
|
| D | constants-arm64.h | 378 UXTX = 3, enumerator
|
| D | simulator-arm64.cc | 882 case UXTX: in ExtendValue()
1717 DCHECK((ext == UXTW) || (ext == UXTX) || (ext == SXTW) || (ext == SXTX)); in VisitLoadStoreRegisterOffset()
|
| D | assembler-arm64.cc | 4305 case UXTX: in EmitExtendShift()
4380 ext = UXTX; in LoadStore()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Utils/ |
| D | AArch64BaseInfo.h | 403 UXTX, enumerator
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1104 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { in printArithExtend()
1108 ExtType == AArch64_AM::UXTX) || in printArithExtend()
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 991 ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX || in isExtend()
1001 return ET != AArch64_AM::UXTX && ET != AArch64_AM::SXTX; in isExtend64()
1007 return (ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX || in isExtendLSL64()
1569 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTX; in addExtend64Operands()
2392 .Case("uxtx", AArch64_AM::UXTX) in tryParseOptionalShiftExtend()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 962 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { in printArithExtend()
966 ExtType == AArch64_AM::UXTX) || in printArithExtend()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 878 return (Shift == 0 || (Shift <= 3 && Ext == AArch64_AM::UXTX)); in isExynosShiftLeftFast()
932 return (Ext == AArch64_AM::SXTX || Ext == AArch64_AM::UXTX); in isExynosShiftLeftFast()
965 case AArch64_AM::UXTX: in isFalkorShiftExtFast()
999 case AArch64_AM::UXTX: in isFalkorShiftExtFast()
1893 return (ExtType != AArch64_AM::UXTX) || AArch64_AM::getMemDoShift(Val); in isScaledAddr()
|
| D | AArch64FrameLowering.cpp | 683 .addImm(AArch64_AM::getArithExtendImm(AArch64_AM::UXTX, 4)) in emitPrologue()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1239 ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX || in isExtend()
1249 return ET != AArch64_AM::UXTX && ET != AArch64_AM::SXTX; in isExtend64()
1256 return (ET == AArch64_AM::UXTX || ET == AArch64_AM::SXTX || in isExtendLSL64()
1723 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTX; in addExtend64Operands()
2669 .Case("uxtx", AArch64_AM::UXTX) in tryParseOptionalShiftExtend()
|
| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 1660 ASSEMBLE_ATOMIC_COMPARE_EXCHANGE_INTEGER(ldaxr, stlxr, UXTX, Register); in AssembleArchInstruction()
|