Searched refs:UseSU (Results 1 – 5 of 5) sorted by relevance
/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
D | ScheduleDAGInstrs.cpp | 301 SUnit *UseSU = UseList[i]; in BuildSchedGraph() local 302 if (UseSU == SU) in BuildSchedGraph() 312 UseSU != &ExitSU) { in BuildSchedGraph() 313 MachineInstr *UseMI = UseSU->getInstr(); in BuildSchedGraph() 328 ComputeOperandLatency(SU, UseSU, const_cast<SDep &>(dep)); in BuildSchedGraph() 329 ST.adjustSchedDependency(SU, UseSU, const_cast<SDep &>(dep)); in BuildSchedGraph() 331 UseSU->addPred(dep); in BuildSchedGraph() 336 SUnit *UseSU = UseList[i]; in BuildSchedGraph() local 337 if (UseSU == SU) in BuildSchedGraph() 341 ComputeOperandLatency(SU, UseSU, const_cast<SDep &>(dep)); in BuildSchedGraph() [all …]
|
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
D | ScheduleDAGInstrs.cpp | 242 SUnit *UseSU = I->SU; in addPhysRegDataDeps() local 243 if (UseSU == SU) in addPhysRegDataDeps() 258 RegUse = UseSU->getInstr(); in addPhysRegDataDeps() 264 ST.adjustSchedDependency(SU, UseSU, Dep); in addPhysRegDataDeps() 265 UseSU->addPred(Dep); in addPhysRegDataDeps() 408 SUnit *UseSU = I->SU; in addVRegDefDeps() local 409 MachineInstr *Use = UseSU->getInstr(); in addVRegDefDeps() 413 ST.adjustSchedDependency(SU, UseSU, Dep); in addVRegDefDeps() 414 UseSU->addPred(Dep); in addVRegDefDeps()
|
D | MachinePipeliner.cpp | 3869 SUnit *UseSU = Insts.at(MoveUse); in orderDependence() local 3878 orderDependence(SSD, UseSU, Insts); in orderDependence() 3903 SUnit *UseSU = SSD->getSUnit(MRI.getVRegDef(LoopVal)); in isLoopCarried() local 3904 if (!UseSU) in isLoopCarried() 3906 if (UseSU->getInstr()->isPHI()) in isLoopCarried() 3908 unsigned LoopCycle = cycleScheduled(UseSU); in isLoopCarried() 3909 int LoopStage = stageScheduled(UseSU); in isLoopCarried()
|
/external/llvm/lib/CodeGen/ |
D | ScheduleDAGInstrs.cpp | 295 SUnit *UseSU = I->SU; in addPhysRegDataDeps() local 296 if (UseSU == SU) in addPhysRegDataDeps() 311 RegUse = UseSU->getInstr(); in addPhysRegDataDeps() 317 ST.adjustSchedDependency(SU, UseSU, Dep); in addPhysRegDataDeps() 318 UseSU->addPred(Dep); in addPhysRegDataDeps() 459 SUnit *UseSU = I->SU; in addVRegDefDeps() local 460 MachineInstr *Use = UseSU->getInstr(); in addVRegDefDeps() 464 ST.adjustSchedDependency(SU, UseSU, Dep); in addVRegDefDeps() 465 UseSU->addPred(Dep); in addVRegDefDeps()
|
D | MachinePipeliner.cpp | 3736 SUnit *UseSU = Insts.at(MoveUse); in orderDependence() local 3745 if (orderDependence(SSD, UseSU, Insts)) { in orderDependence() 3752 Insts.push_back(UseSU); in orderDependence() 3777 SUnit *UseSU = SSD->getSUnit(MRI.getVRegDef(LoopVal)); in isLoopCarried() local 3778 if (!UseSU) in isLoopCarried() 3780 if (UseSU->getInstr()->isPHI()) in isLoopCarried() 3782 unsigned LoopCycle = cycleScheduled(UseSU); in isLoopCarried() 3783 int LoopStage = stageScheduled(UseSU); in isLoopCarried()
|