| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 616 __ abs(v27.V2S(), v25.V2S()); in GenerateTestSequenceNEON()
624 __ add(v15.V2S(), v14.V2S(), v19.V2S()); in GenerateTestSequenceNEON()
629 __ addhn(v10.V2S(), v14.V2D(), v15.V2D()); in GenerateTestSequenceNEON()
638 __ addp(v22.V2S(), v30.V2S(), v26.V2S()); in GenerateTestSequenceNEON()
651 __ bic(v7.V2S(), 0xe4, 16); in GenerateTestSequenceNEON()
663 __ cls(v21.V2S(), v0.V2S()); in GenerateTestSequenceNEON()
669 __ clz(v27.V2S(), v17.V2S()); in GenerateTestSequenceNEON()
680 __ cmeq(v2.V2S(), v3.V2S(), v9.V2S()); in GenerateTestSequenceNEON()
681 __ cmeq(v16.V2S(), v25.V2S(), 0); in GenerateTestSequenceNEON()
696 __ cmge(v25.V2S(), v22.V2S(), v3.V2S()); in GenerateTestSequenceNEON()
[all …]
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| D | test-cpu-features-aarch64.cc | 734 TEST_NEON(abs_4, abs(v0.V2S(), v1.V2S()))
740 TEST_NEON(addhn_2, addhn(v0.V2S(), v1.V2D(), v2.V2D()))
749 TEST_NEON(addp_5, addp(v0.V2S(), v1.V2S(), v2.V2S()))
761 TEST_NEON(add_4, add(v0.V2S(), v1.V2S(), v2.V2S()))
769 TEST_NEON(bic_2, bic(v0.V2S(), 0xd8, 0))
783 TEST_NEON(cls_4, cls(v0.V2S(), v1.V2S()))
789 TEST_NEON(clz_4, clz(v0.V2S(), v1.V2S()))
795 TEST_NEON(cmeq_4, cmeq(v0.V2S(), v1.V2S(), v2.V2S()))
803 TEST_NEON(cmeq_12, cmeq(v0.V2S(), v1.V2S(), 0))
811 TEST_NEON(cmge_4, cmge(v0.V2S(), v1.V2S(), v2.V2S()))
[all …]
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| D | test-disasm-aarch64.cc | 3463 V(V2S(), "2s") \
3469 V(V2S(), "2s", V4H(), "4h") \
3470 V(V1D(), "1d", V2S(), "2s") \
3478 V(V2D(), "2d", V2S(), "2s")
3490 V(V2S(), "2s") \
3496 V(V2S(), "2s") \
3553 COMPARE_MACRO(Ld1(v16.V2S(), in TEST()
3554 v17.V2S(), in TEST()
3555 v18.V2S(), in TEST()
3563 COMPARE_MACRO(Ld1(v19.V2S(), in TEST()
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| D | test-assembler-aarch64.cc | 3755 __ Ld1(v16.V2S(), v17.V2S(), v18.V2S(), v19.V2S(), MemOperand(x17)); in TEST()
3757 __ Ld1(v30.V2S(), v31.V2S(), v0.V2S(), v1.V2S(), MemOperand(x17)); in TEST()
3808 __ Ld1(v16.V2S(), in TEST()
3809 v17.V2S(), in TEST()
3810 v18.V2S(), in TEST()
3811 v19.V2S(), in TEST()
3813 __ Ld1(v30.V2S(), in TEST()
3814 v31.V2S(), in TEST()
3815 v0.V2S(), in TEST()
3816 v1.V2S(), in TEST()
[all …]
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| /external/vixl/src/aarch64/ |
| D | operands-aarch64.h | 370 VRegister V2S() const { return VRegister(code_, kDRegSize, 2); } in V2S() function
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| D | macro-assembler-aarch64.cc | 1067 Movi32bitHelper(vd.Is64Bits() ? vd.V2S() : vd.V4S(), imm & 0xffffffff); in Movi64bitHelper()
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| /external/v8/src/compiler/arm64/ |
| D | code-generator-arm64.cc | 1489 __ Umov(i.OutputRegister32(), i.InputFloat64Register(0).V2S(), 1); in AssembleArchInstruction()
1493 __ Ins(i.OutputFloat64Register().V2S(), 0, i.InputRegister32(1)); in AssembleArchInstruction()
1497 __ Ins(i.OutputFloat64Register().V2S(), 1, i.InputRegister32(1)); in AssembleArchInstruction()
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| /external/v8/src/arm64/ |
| D | macro-assembler-arm64.cc | 481 Movi32bitHelper(vd.Is64Bits() ? vd.V2S() : vd.V4S(), imm & 0xFFFFFFFF); in Movi64bitHelper()
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| D | assembler-arm64.h | 326 VRegister V2S() const { in V2S() function
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 8400 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(), in lowerVectorShuffleAsElementInsertion() local
8402 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) { in lowerVectorShuffleAsElementInsertion()
8404 V2S = DAG.getBitcast(EltVT, V2S); in lowerVectorShuffleAsElementInsertion()
8413 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S); in lowerVectorShuffleAsElementInsertion()
8415 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S); in lowerVectorShuffleAsElementInsertion()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 10748 SDValue V2S = getScalarValueForVectorElement(V2, Mask[V2Index] - Mask.size(), in lowerVectorShuffleAsElementInsertion() local
10750 if (V2S && DAG.getTargetLoweringInfo().isTypeLegal(V2S.getValueType())) { in lowerVectorShuffleAsElementInsertion()
10752 V2S = DAG.getBitcast(EltVT, V2S); in lowerVectorShuffleAsElementInsertion()
10761 V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S); in lowerVectorShuffleAsElementInsertion()
10763 V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S); in lowerVectorShuffleAsElementInsertion()
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