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Searched refs:VALIGNADDR (Results 1 – 4 of 4) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonISelLowering.h88 VALIGNADDR, // Align vector address: Op0 & -Op1, except when it is enumerator
DHexagonISelLowering.cpp1735 case HexagonISD::VALIGNADDR: return "HexagonISD::VALIGNADDR"; in getTargetNodeName()
2695 if (BaseOpc == HexagonISD::VALIGNADDR && BO.second % LoadLen == 0) in LowerUnalignedLoad()
2703 SDValue BaseNoOff = (BaseOpc != HexagonISD::VALIGNADDR) in LowerUnalignedLoad()
2704 ? DAG.getNode(HexagonISD::VALIGNADDR, dl, MVT::i32, BO.first, in LowerUnalignedLoad()
DHexagonISelDAGToDAG.cpp891 case HexagonISD::VALIGNADDR: return SelectVAlignAddr(N); in Select()
DHexagonPatterns.td108 def HexagonVALIGNADDR: SDNode<"HexagonISD::VALIGNADDR", SDTIntUnaryOp>;