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Searched refs:VEC (Results 1 – 25 of 44) sorted by relevance

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/external/llvm/test/Transforms/LoopVectorize/
Dif-pred-stores.ll3 …orize -enable-cond-stores-vec -verify-loop-info -simplifycfg < %s | FileCheck %s --check-prefix=VEC
4 …nd-stores-vec -verify-loop-info -simplifycfg -instcombine < %s | FileCheck %s --check-prefix=VEC-IC
14 ; VEC-LABEL: test
15 ; VEC: %[[v8:.+]] = icmp sgt <2 x i32> %{{.*}}, <i32 100, i32 100>
16 ; VEC: %[[v9:.+]] = add nsw <2 x i32> %{{.*}}, <i32 20, i32 20>
17 ; VEC: %[[v10:.+]] = and <2 x i1> %[[v8]], <i1 true, i1 true>
18 ; VEC: %[[v11:.+]] = extractelement <2 x i1> %[[v10]], i32 0
19 ; VEC: %[[v12:.+]] = icmp eq i1 %[[v11]], true
20 ; VEC: %[[v13:.+]] = extractelement <2 x i32> %[[v9]], i32 0
21 ; VEC: %[[v14:.+]] = extractelement <2 x i32*> %{{.*}}, i32 0
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopVectorize/
Dif-pred-stores.ll3 …-interleave=1 -loop-vectorize -verify-loop-info -simplifycfg < %s | FileCheck %s --check-prefix=VEC
12 ; VEC-LABEL: test
13 ; VEC: %[[v0:.+]] = add i64 %index, 0
14 ; VEC: %[[v2:.+]] = getelementptr inbounds i32, i32* %f, i64 %[[v0]]
15 ; VEC: %[[v8:.+]] = icmp sgt <2 x i32> %{{.*}}, <i32 100, i32 100>
16 ; VEC: %[[v11:.+]] = extractelement <2 x i1> %[[v8]], i32 0
17 ; VEC: br i1 %[[v11]], label %[[cond:.+]], label %[[else:.+]]
19 ; VEC: [[cond]]:
20 ; VEC: %[[v13:.+]] = extractelement <2 x i32> %wide.load, i32 0
21 ; VEC: %[[v9a:.+]] = add nsw i32 %[[v13]], 20
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Generic/
Dexpand-experimental-reductions.ll25 ; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <2 x i64> [[VEC:%.*]], <2 x i64> undef, <2 x i32>…
26 ; CHECK-NEXT: [[BIN_RDX:%.*]] = add <2 x i64> [[VEC]], [[RDX_SHUF]]
38 ; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <2 x i64> [[VEC:%.*]], <2 x i64> undef, <2 x i32>…
39 ; CHECK-NEXT: [[BIN_RDX:%.*]] = mul <2 x i64> [[VEC]], [[RDX_SHUF]]
51 ; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <2 x i64> [[VEC:%.*]], <2 x i64> undef, <2 x i32>…
52 ; CHECK-NEXT: [[BIN_RDX:%.*]] = and <2 x i64> [[VEC]], [[RDX_SHUF]]
64 ; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <2 x i64> [[VEC:%.*]], <2 x i64> undef, <2 x i32>…
65 ; CHECK-NEXT: [[BIN_RDX:%.*]] = or <2 x i64> [[VEC]], [[RDX_SHUF]]
77 ; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <2 x i64> [[VEC:%.*]], <2 x i64> undef, <2 x i32>…
78 ; CHECK-NEXT: [[BIN_RDX:%.*]] = xor <2 x i64> [[VEC]], [[RDX_SHUF]]
[all …]
/external/llvm/test/Transforms/LoopVectorize/AArch64/
Darbitrary-induction-step.ll2 …-vectorize -force-vector-interleave=1 -force-vector-width=2 | FileCheck %s --check-prefix=FORCE-VEC
23 ; FORCE-VEC-LABEL: @ind_plus2(
24 ; FORCE-VEC: %wide.load = load <2 x i32>, <2 x i32>*
25 ; FORCE-VEC: mul nsw <2 x i32>
26 ; FORCE-VEC: add nsw <2 x i32>
27 ; FORCE-VEC: %index.next = add i64 %index, 2
28 ; FORCE-VEC: icmp eq i64 %index.next, 512
67 ; FORCE-VEC-LABEL: @ind_minus2(
68 ; FORCE-VEC: %wide.load = load <2 x i32>, <2 x i32>*
69 ; FORCE-VEC: mul nsw <2 x i32>
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopVectorize/AArch64/
Darbitrary-induction-step.ll2 …-vectorize -force-vector-interleave=1 -force-vector-width=2 | FileCheck %s --check-prefix=FORCE-VEC
23 ; FORCE-VEC-LABEL: @ind_plus2(
24 ; FORCE-VEC: %wide.load = load <2 x i32>, <2 x i32>*
25 ; FORCE-VEC: mul nsw <2 x i32>
26 ; FORCE-VEC: add nsw <2 x i32>
27 ; FORCE-VEC: %index.next = add i64 %index, 2
28 ; FORCE-VEC: icmp eq i64 %index.next, 512
67 ; FORCE-VEC-LABEL: @ind_minus2(
68 ; FORCE-VEC: %wide.load = load <2 x i32>, <2 x i32>*
69 ; FORCE-VEC: mul nsw <2 x i32>
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dvec-args-01.ll3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
16 ; CHECK-VEC-LABEL: foo:
17 ; CHECK-VEC-DAG: vrepif %v24, 1
18 ; CHECK-VEC-DAG: vrepif %v26, 2
19 ; CHECK-VEC-DAG: vrepif %v28, 3
20 ; CHECK-VEC-DAG: vrepif %v30, 4
21 ; CHECK-VEC-DAG: vrepif %v25, 5
22 ; CHECK-VEC-DAG: vrepif %v27, 6
23 ; CHECK-VEC-DAG: vrepif %v29, 7
24 ; CHECK-VEC-DAG: vrepif %v31, 8
[all …]
Dvec-args-04.ll3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
13 ; CHECK-VEC-LABEL: foo:
14 ; CHECK-VEC-DAG: vrepib %v24, 1
15 ; CHECK-VEC-DAG: vrepib %v26, 2
16 ; CHECK-VEC-DAG: vrepib %v28, 3
17 ; CHECK-VEC-DAG: vrepib %v30, 4
18 ; CHECK-VEC-DAG: vrepib %v25, 5
19 ; CHECK-VEC-DAG: vrepib %v27, 6
20 ; CHECK-VEC-DAG: vrepib %v29, 7
21 ; CHECK-VEC-DAG: vrepib %v31, 8
[all …]
Dvec-args-02.ll3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
12 ; CHECK-VEC-LABEL: foo:
13 ; CHECK-VEC-DAG: vrepif %v24, 1
14 ; CHECK-VEC-DAG: vrepif %v26, 2
15 ; CHECK-VEC: brasl %r14, bar@PLT
Dvec-args-05.ll3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
12 ; CHECK-VEC-LABEL: foo:
13 ; CHECK-VEC-DAG: vrepib %v24, 1
14 ; CHECK-VEC-DAG: vrepib %v26, 2
15 ; CHECK-VEC: brasl %r14, bar@PLT
/external/llvm/test/CodeGen/SystemZ/
Dvec-args-01.ll3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
16 ; CHECK-VEC-LABEL: foo:
17 ; CHECK-VEC-DAG: vrepif %v24, 1
18 ; CHECK-VEC-DAG: vrepif %v26, 2
19 ; CHECK-VEC-DAG: vrepif %v28, 3
20 ; CHECK-VEC-DAG: vrepif %v30, 4
21 ; CHECK-VEC-DAG: vrepif %v25, 5
22 ; CHECK-VEC-DAG: vrepif %v27, 6
23 ; CHECK-VEC-DAG: vrepif %v29, 7
24 ; CHECK-VEC-DAG: vrepif %v31, 8
[all …]
Dvec-args-04.ll3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
13 ; CHECK-VEC-LABEL: foo:
14 ; CHECK-VEC-DAG: vrepib %v24, 1
15 ; CHECK-VEC-DAG: vrepib %v26, 2
16 ; CHECK-VEC-DAG: vrepib %v28, 3
17 ; CHECK-VEC-DAG: vrepib %v30, 4
18 ; CHECK-VEC-DAG: vrepib %v25, 5
19 ; CHECK-VEC-DAG: vrepib %v27, 6
20 ; CHECK-VEC-DAG: vrepib %v29, 7
21 ; CHECK-VEC-DAG: vrepib %v31, 8
[all …]
Dvec-args-02.ll3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
12 ; CHECK-VEC-LABEL: foo:
13 ; CHECK-VEC-DAG: vrepif %v24, 1
14 ; CHECK-VEC-DAG: vrepif %v26, 2
15 ; CHECK-VEC: brasl %r14, bar@PLT
Dvec-args-05.ll3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s -check-prefix=CHECK-VEC
12 ; CHECK-VEC-LABEL: foo:
13 ; CHECK-VEC-DAG: vrepib %v24, 1
14 ; CHECK-VEC-DAG: vrepib %v26, 2
15 ; CHECK-VEC: brasl %r14, bar@PLT
/external/llvm/test/Transforms/InstCombine/
Dsincospi.ll1 …stcombine -S < %s -mtriple=x86_64-apple-macosx10.9 | FileCheck %s --check-prefix=CHECK-FLOAT-IN-VEC
26 ; CHECK-FLOAT-IN-VEC: [[VAL:%[a-z0-9]+]] = load float, float* @var32
27 ; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call <2 x float> @__sincospif_stret(float [[VAL]])
28 ; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 0
29 ; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 1
45 ; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call <2 x float> @__sincospif_stret(float 1.000000e+0…
46 ; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 0
47 ; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 1
63 ; CHECK-FLOAT-IN-VEC: [[VAL:%[a-z0-9]+]] = load double, double* @var64
64 ; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call { double, double } @__sincospi_stret(double [[VA…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dsincospi.ll1 …stcombine -S < %s -mtriple=x86_64-apple-macosx10.9 | FileCheck %s --check-prefix=CHECK-FLOAT-IN-VEC
26 ; CHECK-FLOAT-IN-VEC: [[VAL:%[a-z0-9]+]] = load float, float* @var32
27 ; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call <2 x float> @__sincospif_stret(float [[VAL]])
28 ; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 0
29 ; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 1
45 ; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call <2 x float> @__sincospif_stret(float 1.000000e+0…
46 ; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 0
47 ; CHECK-FLOAT-IN-VEC: extractelement <2 x float> [[SINCOS]], i32 1
63 ; CHECK-FLOAT-IN-VEC: [[VAL:%[a-z0-9]+]] = load double, double* @var64
64 ; CHECK-FLOAT-IN-VEC: [[SINCOS:%[a-z0-9]+]] = call { double, double } @__sincospi_stret(double [[VA…
[all …]
Dicmp-bc-vec.ll77 ; CHECK-NEXT: [[VEC:%.*]] = shufflevector <4 x i8> [[INVEC:%.*]], <4 x i8> undef, <4 x i32> <i32…
78 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i8> [[VEC]] to i32
92 ; CHECK-NEXT: [[VEC:%.*]] = shufflevector <4 x i8> [[INSVEC]], <4 x i8> undef, <4 x i32> zeroini…
93 ; CHECK-NEXT: [[CAST:%.*]] = bitcast <4 x i8> [[VEC]] to i32
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dinsert_vector_elt.v2i16.ll6 ; GCN: s_load_dword [[VEC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x0
8 ; CIVI: s_and_b32 [[ELT1:s[0-9]+]], [[VEC]], 0xffff0000{{$}}
12 ; GFX9: s_pack_lh_b32_b16 s{{[0-9]+}}, 0x3e7, [[VEC]]
22 ; GCN-DAG: s_load_dword [[VEC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x0
25 ; CIVI-DAG: s_and_b32 [[ELT1:s[0-9]+]], [[VEC]], 0xffff0000{{$}}
29 ; GFX9-NOT: [[VEC]]
30 ; GFX9: s_pack_lh_b32_b16 s{{[0-9]+}}, [[ELT_LOAD]], [[VEC]]
40 ; GCN-DAG: s_load_dword [[VEC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x0
43 ; CI: s_lshr_b32 [[SHR:s[0-9]+]], [[VEC]], 16
51 ; VI-DAG: s_and_b32 [[VEC_HIMASK:s[0-9]+]], [[VEC]], 0xffff0000{{$}}
[all …]
Dextract_vector_elt-i16.ll6 ; GCN: s_load_dword [[VEC:s[0-9]+]]
7 ; GCN: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], 16
8 ; GCN-DAG: v_mov_b32_e32 [[VELT0:v[0-9]+]], [[VEC]]
24 ; GCN: s_load_dword [[VEC:s[0-9]+]]
26 ; GCN: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], [[IDX_SCALED]]
38 ; GCN-DAG: s_load_dword [[VEC:s[0-9]+]]
42 ; SI: v_lshr_b32_e32 [[ELT:v[0-9]+]], [[VEC]], [[IDX_SCALED]]
43 ; VI: v_lshrrev_b32_e64 [[ELT:v[0-9]+]], [[IDX_SCALED]], [[VEC]]
Dextract_vector_elt-f16.ll5 ; GCN: s_load_dword [[VEC:s[0-9]+]]
6 ; GCN: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], 16
7 ; GCN-DAG: v_mov_b32_e32 [[VELT0:v[0-9]+]], [[VEC]]
23 ; GCN: s_load_dword [[VEC:s[0-9]+]]
25 ; GCN: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], [[IDX_SCALED]]
37 ; GCN-DAG: s_load_dword [[VEC:s[0-9]+]]
41 ; SI: v_lshr_b32_e32 [[ELT:v[0-9]+]], [[VEC]], [[IDX_SCALED]]
42 ; VI: v_lshrrev_b32_e64 [[ELT:v[0-9]+]], [[IDX_SCALED]], [[VEC]]
/external/mesa3d/src/gallium/drivers/nouveau/nv30/
Dnvfx_vertprog.c497 nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, in nvfx_vertprog_parse_instruction()
508 nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, in nvfx_vertprog_parse_instruction()
519 nvfx_vp_emit(vpc, arith(0, VEC, MOV, src[i].reg, NVFX_VP_MASK_ALL, in nvfx_vertprog_parse_instruction()
554 nvfx_vp_emit(vpc, arith(sat, VEC, ADD, dst, mask, src[0], none, src[1])); in nvfx_vertprog_parse_instruction()
557 nvfx_vp_emit(vpc, arith(0, VEC, ARL, dst, mask, src[0], none, none)); in nvfx_vertprog_parse_instruction()
561 nvfx_vp_emit(vpc, arith(0, VEC, FLR, tmp.reg, mask, neg(src[0]), none, none)); in nvfx_vertprog_parse_instruction()
562 nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, neg(tmp), none, none)); in nvfx_vertprog_parse_instruction()
565 insn = arith(0, VEC, MOV, none.reg, mask, src[0], none, none); in nvfx_vertprog_parse_instruction()
569 insn = arith(sat, VEC, MOV, dst, mask, src[2], none, none); in nvfx_vertprog_parse_instruction()
573 insn = arith(sat, VEC, MOV, dst, mask, src[1], none, none); in nvfx_vertprog_parse_instruction()
[all …]
/external/llvm/unittests/Transforms/Utils/
DASanStackFrameLayoutTest.cpp42 #define VEC(a) \ in TEST() macro
88 TestLayout(VEC(t), 8, 32, in TEST()
95 TestLayout(VEC(t), 8, 32, in TEST()
100 #undef VEC in TEST()
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/ValueTracking/
Dsignbits-extract-elt.ll20 ; CHECK-NEXT: [[VEC:%.*]] = sext <2 x i1> [[VEC:%.*]]in to <2 x i32>
21 ; CHECK-NEXT: [[ELT0:%.*]] = extractelement <2 x i32> [[VEC]], i32 0
/external/antlr/runtime/CSharp3/Sources/Antlr3.Runtime.Test/Composition/
DSimplify.g315 : ^( MULT INT ^(VEC (e+=.)+) ) -> ^(VEC ^(MULT INT $e)+)
DVecMath_Parser.g39 VEC;
32 | OPEN_SQUARE expr ( COMMA expr )* CLOSE_SQUARE -> ^( VEC expr+ )
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/AArch64/
Dtbl1.ll15 ; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <16 x i8> [[VEC:%.*]], <16 x i8> undef, <8 x i32> <i3…
27 ; CHECK-NEXT: [[TBL1:%.*]] = call <8 x i8> @llvm.aarch64.neon.tbl1.v8i8(<16 x i8> [[VEC:%.*]], <…
39 ; CHECK-NEXT: [[TBL1:%.*]] = call <16 x i8> @llvm.aarch64.neon.tbl1.v16i8(<16 x i8> [[VEC:%.*]],…
51 ; CHECK-NEXT: [[TBL1:%.*]] = call <8 x i16> @llvm.aarch64.neon.tbl1.v8i16(<16 x i8> [[VEC:%.*]],…

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