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Searched refs:VGPR (Results 1 – 25 of 64) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dspill-wide-sgpr.ll1 …spill-sgpr-to-smem=0 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=VGPR %s
20 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
21 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
22 ; VGPR: s_cbranch_scc1
24 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
25 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
59 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
60 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
61 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2
62 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 3
[all …]
Dcontrol-flow-fastregalloc.ll2 …=1 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=VGPR -check-prefix=GCN %s
8 ; FIXME: This checks with SGPR to VGPR spilling disabled, but this may
13 ; VGPR: workitem_private_segment_byte_size = 12{{$}}
25 ; VGPR: v_writelane_b32 [[SPILL_VGPR:v[0-9]+]], s[[SAVEEXEC_LO]], [[SAVEEXEC_LO_LANE:[0-9]+]]
26 ; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[SAVEEXEC_HI]], [[SAVEEXEC_HI_LANE:[0-9]+]]
55 ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]]
56 ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]]
93 ; VGPR: workitem_private_segment_byte_size = 16{{$}}
109 ; VGPR: v_writelane_b32 [[SPILL_VGPR:v[0-9]+]], s[[SAVEEXEC_LO]], [[SAVEEXEC_LO_LANE:[0-9]+]]
110 ; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[SAVEEXEC_HI]], [[SAVEEXEC_HI_LANE:[0-9]+]]
[all …]
Dillegal-sgpr-to-vgpr-copy.ll4 … error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_i32 void (): illegal SGPR to VGPR copy
13 …rror: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v2i32 void (): illegal SGPR to VGPR copy
21 …rror: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v4i32 void (): illegal SGPR to VGPR copy
29 …rror: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v8i32 void (): illegal SGPR to VGPR copy
37 …ror: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v16i32 void (): illegal SGPR to VGPR copy
Dspill-scavenge-offset.ll8 ; When the offset of VGPR spills into scratch space gets too large, an additional SGPR
22 ; mark most VGPR registers as used to increase register pressure
Dadd_i64.ll20 ; Check that the SGPR add operand is correctly moved to a VGPR.
31 ; Swap the arguments. Check that the SGPR -> VGPR copy works with the
Dsgpr-copy-duplicate-operand.ll4 ; Copy VGPR -> SGPR used twice as an instruction operand, which is then
Dtrunc-store-i1.ll24 ; FIXME: VGPR on VI
Dhoist-cond.ll4 ; At the same time condition shall not be serialized into a VGPR and deserialized later
/external/llvm/include/llvm/IR/
DIntrinsicsAMDGPU.td191 [llvm_v4f32_ty], // vdata(VGPR)
192 [llvm_anyint_ty, // vaddr(VGPR)
206 [llvm_v4f32_ty, // vdata(VGPR)
207 llvm_anyint_ty, // vaddr(VGPR)
221 [llvm_i32_ty, // vdata(VGPR)
222 llvm_anyint_ty, // vaddr(VGPR)
243 [llvm_i32_ty, // src(VGPR)
244 llvm_i32_ty, // cmp(VGPR)
245 llvm_anyint_ty, // vaddr(VGPR)
255 llvm_i32_ty, // vindex(VGPR)
[all …]
/external/llvm/lib/Target/AMDGPU/
DSIIntrinsics.td25 llvm_anyint_ty, // vdata(VGPR), overloaded for types i32, v2i32, v4i32
27 llvm_i32_ty, // vaddr(VGPR)
41 [llvm_anyint_ty], // vdata(VGPR), overloaded for types i32, v2i32, v4i32
43 llvm_anyint_ty, // vaddr(VGPR)
57 [llvm_v4f32_ty], // vdata(VGPR)
58 [llvm_anyint_ty, // vaddr(VGPR)
73 [llvm_v4f32_ty], // vdata(VGPR)
74 [llvm_anyint_ty, // vaddr(VGPR)
DSIRegisterInfo.td107 // VGPR registers
109 def VGPR#Index : SIReg <"VGPR"#Index, Index> {
192 // VGPR 32-bit registers
194 (add (sequence "VGPR%u", 0, 255))> {
198 // VGPR 64-bit registers
203 // VGPR 96-bit registers
209 // VGPR 128-bit registers
216 // VGPR 256-bit registers
227 // VGPR 512-bit registers
378 // VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate
[all …]
DSIMachineFunctionInfo.h124 unsigned VGPR; member
126 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { } in SpilledReg()
127 SpilledReg() : VGPR(AMDGPU::NoRegister), Lane(-1) { } in SpilledReg()
129 bool hasReg() { return VGPR != AMDGPU::NoRegister;} in hasReg()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIIntrinsics.td23 llvm_anyint_ty, // vdata(VGPR), overloaded for types i32, v2i32, v4i32
25 llvm_i32_ty, // vaddr(VGPR)
39 [llvm_anyint_ty], // vdata(VGPR), overloaded for types i32, v2i32, v4i32
41 llvm_anyint_ty, // vaddr(VGPR)
DSIRegisterInfo.td142 // VGPR registers
144 def VGPR#Index : SIReg <"VGPR"#Index, Index> {
168 // Give all SGPR classes higher priority than VGPR classes, because
341 // VGPR 32-bit registers
344 (add (sequence "VGPR%u", 0, 255))> {
349 // VGPR 64-bit registers
354 // VGPR 96-bit registers
360 // VGPR 128-bit registers
367 // VGPR 256-bit registers
378 // VGPR 512-bit registers
[all …]
DSIMachineFunctionInfo.h195 unsigned VGPR = 0; member
199 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) {} in SpilledReg()
202 bool hasReg() { return VGPR != 0;} in hasReg()
207 unsigned VGPR; member
213 SGPRSpillVGPRCSR(unsigned V, Optional<int> F) : VGPR(V), FI(F) {} in SGPRSpillVGPRCSR()
DAMDGPURegisterBanks.td14 def VGPRRegBank : RegisterBank<"VGPR",
DAMDGPUCallingConv.td89 (sequence "VGPR%u", 24, 255)
93 (sequence "VGPR%u", 32, 255)
/external/clang/test/SemaOpenCL/
Damdgpu-num-register-attrs.cl20 // Check 0 VGPR is accepted.
26 // Check both 0 SGPR and VGPR is accepted.
29 // Too large VGPR value.
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dinst-select-sitofp.mir20 ; GCN: [[VGPR:%[0-9]+]]:vgpr_32 = COPY $vgpr0
30 ; GCN: V_CVT_F32_I32_e64 [[VGPR]], 0, 0
Dinst-select-fptoui.mir20 ; GCN: [[VGPR:%[0-9]+]]:vgpr_32 = COPY $vgpr0
30 ; GCN: V_CVT_U32_F32_e64 0, [[VGPR]], 0, 0
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/
DIntrinsicsAMDGPU.td628 P_.RetTypes, // vdata(VGPR) -- for load/atomic-with-return
630 !foreach(arg, P_.DataArgs, arg.Type), // vdata(VGPR) -- for store/atomic
632 P_.AddrTypes, // vaddr(VGPR)
796 llvm_i32_ty, // vindex(VGPR)
797 llvm_i32_ty, // offset(SGPR/VGPR/imm)
807 [llvm_anyfloat_ty, // vdata(VGPR) -- can currently only select f32, v2f32, v4f32
809 llvm_i32_ty, // vindex(VGPR)
810 llvm_i32_ty, // offset(SGPR/VGPR/imm)
821 llvm_i32_ty, // vindex(VGPR)
822 llvm_i32_ty, // voffset(VGPR)
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dspill-scavenge-offset.ll8 ; When the offset of VGPR spills into scratch space gets too large, an additional SGPR
22 ; mark most VGPR registers as used to increase register pressure
Dadd_i64.ll20 ; Check that the SGPR add operand is correctly moved to a VGPR.
31 ; Swap the arguments. Check that the SGPR -> VGPR copy works with the
Dsgpr-copy-duplicate-operand.ll4 ; Copy VGPR -> SGPR used twice as an instruction operand, which is then
Dadd.ll141 ; %0 will be stored in a VGPR, so the comiler will be forced to copy %a
142 ; to a VGPR before doing the add.

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