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Searched refs:VGPR0 (Results 1 – 21 of 21) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dinst-select-amdgcn.cvt.pkrtz.mir19 ; GCN: [[VGPR0:%[0-9]+]]:vgpr_32 = COPY $vgpr0
26 ; GCN: V_CVT_PKRTZ_F16_F32_e32 [[SGPR0]], [[VGPR0]]
30 ; GCN: V_CVT_PKRTZ_F16_F32_e32 [[SGPR0]], [[VGPR0]]
34 ; GCN: V_CVT_PKRTZ_F16_F32_e32 [[VGPR0]], [[VGPR1]]
Dinst-select-minnum.mir17 ; GCN: [[VGPR0:%[0-9]+]]:vgpr_32 = COPY $vgpr0
32 ; GCN: V_MIN_F32_e32 [[SGPR0]], [[VGPR0]]
36 ; GCN: V_MIN_F32_e32 [[SGPR0]], [[VGPR0]]
40 ; GCN: V_MIN_F32_e32 [[VGPR0]], [[VGPR1]]
Dinst-select-maxnum.mir17 ; GCN: [[VGPR0:%[0-9]+]]:vgpr_32 = COPY $vgpr0
32 ; GCN: V_MAX_F32_e32 [[SGPR0]], [[VGPR0]]
36 ; GCN: V_MAX_F32_e32 [[SGPR0]], [[VGPR0]]
40 ; GCN: V_MAX_F32_e32 [[VGPR0]], [[VGPR1]]
Dinst-select-ashr.mir19 ; GCN: [[VGPR0:%[0-9]+]]:vgpr_32 = COPY $vgpr0
51 ; GCN: [[VS:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e32 [[CS]], [[VGPR0]]
60 ; SI: [[VV:%[0-9]+]]:vgpr_32 = V_ASHR_I32_e32 [[SV]], [[VGPR0]]
61 ; VI: [[VV:%[0-9]+]]:vgpr_32 = V_ASHRREV_I32_e32 [[VGPR0]], [[SV]]
Dinst-select-or.mir18 ; GCN: [[VGPR0:%[0-9]+]]:vgpr_32 = COPY $vgpr0
31 ; GCN: [[VS:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[SS]], [[VGPR0]]
39 ; GCN: [[VV:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[SV]], [[VGPR0]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.mov.dpp.ll22 ; VI: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s{{[0-9]+}}
26 ; VI-OPT: v_mov_b32_dpp [[VGPR0]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_c…
27 ; VI-NOOPT: v_mov_b32_dpp [[VGPR1]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound…
31 ; VI-OPT: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound…
46 ; VI: v_mov_b32_dpp [[VGPR0:v[0-9]+]], v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 b…
48 ; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou…
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.mov.dpp.ll17 ; VI: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s{{[0-9]+}}
19 ; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou…
34 ; VI: v_mov_b32_dpp [[VGPR0:v[0-9]+]], v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 b…
36 ; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bou…
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInsertSkips.cpp169 .addReg(AMDGPU::VGPR0, RegState::Undef) in skipIfDead()
170 .addReg(AMDGPU::VGPR0, RegState::Undef) in skipIfDead()
171 .addReg(AMDGPU::VGPR0, RegState::Undef) in skipIfDead()
172 .addReg(AMDGPU::VGPR0, RegState::Undef) in skipIfDead()
DAMDGPUCallingConv.td37 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
68 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
110 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
127 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
DSIInsertWaitcnts.cpp91 unsigned VGPR0; member
493 assert(Reg >= RegisterEncoding.VGPR0 && Reg <= RegisterEncoding.VGPRL); in getRegInterval()
494 Result.first = Reg - RegisterEncoding.VGPR0; in getRegInterval()
1863 RegisterEncoding.VGPR0 = TRI->getEncodingValue(AMDGPU::VGPR0); in runOnMachineFunction()
1865 RegisterEncoding.VGPR0 + HardwareLimits.NumVGPRsMax - 1; in runOnMachineFunction()
DSIMachineFunctionInfo.cpp319 return AMDGPU::VGPR0; in getWorkItemIDVGPR()
DSIRegisterInfo.cpp77 classifyPressureSet(i, AMDGPU::VGPR0, VGPRPressureSets); in SIRegisterInfo()
1173 REG_RANGE(AMDGPU::VGPR0, AMDGPU::VGPR255, VGPR32RegNames); in getRegAsmName()
DSOPInstructions.td620 // VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
DSIISelLowering.cpp1397 unsigned Reg = AMDGPU::VGPR0; in allocateSpecialEntryInputVGPRs()
1810 CCInfo.AllocateReg(AMDGPU::VGPR0); in LowerFormalArguments()
/external/llvm/lib/Target/AMDGPU/
DAMDGPUCallingConv.td39 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
80 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
DSILowerControlFlow.cpp237 .addReg(AMDGPU::VGPR0, RegState::Undef) in skipIfDead()
238 .addReg(AMDGPU::VGPR0, RegState::Undef) in skipIfDead()
239 .addReg(AMDGPU::VGPR0, RegState::Undef) in skipIfDead()
240 .addReg(AMDGPU::VGPR0, RegState::Undef); in skipIfDead()
DSIMachineFunctionInfo.h405 return AMDGPU::VGPR0; in getWorkItemIDVGPR()
DSIRegisterInfo.cpp107 classifyPressureSet(i, AMDGPU::VGPR0, VGPRPressureSets); in SIRegisterInfo()
946 return AMDGPU::VGPR0; in getPreloadedValue()
DSIInstructions.td370 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
DSIISelLowering.cpp678 CCInfo.AllocateReg(AMDGPU::VGPR0); in LowerFormalArguments()
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DAMDGPUUsage.rst2329 for enabled registers are dense starting at VGPR0: the first enabled register is
2330 VGPR0, the next enabled register is VGPR1 etc.; disabled registers do not have a
3851 ``VGPR0``: intrinsic (not