1 /********************************************************** 2 * Copyright 2007-2015 VMware, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person 5 * obtaining a copy of this software and associated documentation 6 * files (the "Software"), to deal in the Software without 7 * restriction, including without limitation the rights to use, copy, 8 * modify, merge, publish, distribute, sublicense, and/or sell copies 9 * of the Software, and to permit persons to whom the Software is 10 * furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be 13 * included in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 * 24 **********************************************************/ 25 26 /* 27 * VGPU10ShaderTokens.h -- 28 * 29 * VGPU10 shader token definitions. 30 * 31 */ 32 33 #ifndef VGPU10SHADERTOKENS_H 34 #define VGPU10SHADERTOKENS_H 35 36 /* Shader limits */ 37 #define VGPU10_MAX_VS_INPUTS 16 38 #define VGPU10_MAX_VS_OUTPUTS 16 39 #define VGPU10_MAX_GS_INPUTS 16 40 #define VGPU10_MAX_GS_OUTPUTS 32 41 #define VGPU10_MAX_FS_INPUTS 32 42 #define VGPU10_MAX_FS_OUTPUTS 8 43 #define VGPU10_MAX_TEMPS 4096 44 #define VGPU10_MAX_CONSTANT_BUFFERS 14 45 #define VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT 4096 46 #define VGPU10_MAX_IMMEDIATE_CONSTANT_BUFFER_ELEMENT_COUNT 4096 47 #define VGPU10_MAX_SAMPLERS 16 48 #define VGPU10_MAX_RESOURCES 128 49 #define VGPU10_MIN_TEXEL_FETCH_OFFSET -8 50 #define VGPU10_MAX_TEXEL_FETCH_OFFSET 7 51 52 typedef enum { 53 VGPU10_PIXEL_SHADER = 0, 54 VGPU10_VERTEX_SHADER = 1, 55 VGPU10_GEOMETRY_SHADER = 2 56 } VGPU10_PROGRAM_TYPE; 57 58 typedef union { 59 struct { 60 unsigned int minorVersion : 4; 61 unsigned int majorVersion : 4; 62 unsigned int : 8; 63 unsigned int programType : 16; /* VGPU10_PROGRAM_TYPE */ 64 }; 65 uint32 value; 66 } VGPU10ProgramToken; 67 68 69 typedef enum { 70 VGPU10_OPCODE_ADD = 0, 71 VGPU10_OPCODE_AND = 1, 72 VGPU10_OPCODE_BREAK = 2, 73 VGPU10_OPCODE_BREAKC = 3, 74 VGPU10_OPCODE_CALL = 4, 75 VGPU10_OPCODE_CALLC = 5, 76 VGPU10_OPCODE_CASE = 6, 77 VGPU10_OPCODE_CONTINUE = 7, 78 VGPU10_OPCODE_CONTINUEC = 8, 79 VGPU10_OPCODE_CUT = 9, 80 VGPU10_OPCODE_DEFAULT = 10, 81 VGPU10_OPCODE_DERIV_RTX = 11, 82 VGPU10_OPCODE_DERIV_RTY = 12, 83 VGPU10_OPCODE_DISCARD = 13, 84 VGPU10_OPCODE_DIV = 14, 85 VGPU10_OPCODE_DP2 = 15, 86 VGPU10_OPCODE_DP3 = 16, 87 VGPU10_OPCODE_DP4 = 17, 88 VGPU10_OPCODE_ELSE = 18, 89 VGPU10_OPCODE_EMIT = 19, 90 VGPU10_OPCODE_EMITTHENCUT = 20, 91 VGPU10_OPCODE_ENDIF = 21, 92 VGPU10_OPCODE_ENDLOOP = 22, 93 VGPU10_OPCODE_ENDSWITCH = 23, 94 VGPU10_OPCODE_EQ = 24, 95 VGPU10_OPCODE_EXP = 25, 96 VGPU10_OPCODE_FRC = 26, 97 VGPU10_OPCODE_FTOI = 27, 98 VGPU10_OPCODE_FTOU = 28, 99 VGPU10_OPCODE_GE = 29, 100 VGPU10_OPCODE_IADD = 30, 101 VGPU10_OPCODE_IF = 31, 102 VGPU10_OPCODE_IEQ = 32, 103 VGPU10_OPCODE_IGE = 33, 104 VGPU10_OPCODE_ILT = 34, 105 VGPU10_OPCODE_IMAD = 35, 106 VGPU10_OPCODE_IMAX = 36, 107 VGPU10_OPCODE_IMIN = 37, 108 VGPU10_OPCODE_IMUL = 38, 109 VGPU10_OPCODE_INE = 39, 110 VGPU10_OPCODE_INEG = 40, 111 VGPU10_OPCODE_ISHL = 41, 112 VGPU10_OPCODE_ISHR = 42, 113 VGPU10_OPCODE_ITOF = 43, 114 VGPU10_OPCODE_LABEL = 44, 115 VGPU10_OPCODE_LD = 45, 116 VGPU10_OPCODE_LD_MS = 46, 117 VGPU10_OPCODE_LOG = 47, 118 VGPU10_OPCODE_LOOP = 48, 119 VGPU10_OPCODE_LT = 49, 120 VGPU10_OPCODE_MAD = 50, 121 VGPU10_OPCODE_MIN = 51, 122 VGPU10_OPCODE_MAX = 52, 123 VGPU10_OPCODE_CUSTOMDATA = 53, 124 VGPU10_OPCODE_MOV = 54, 125 VGPU10_OPCODE_MOVC = 55, 126 VGPU10_OPCODE_MUL = 56, 127 VGPU10_OPCODE_NE = 57, 128 VGPU10_OPCODE_NOP = 58, 129 VGPU10_OPCODE_NOT = 59, 130 VGPU10_OPCODE_OR = 60, 131 VGPU10_OPCODE_RESINFO = 61, 132 VGPU10_OPCODE_RET = 62, 133 VGPU10_OPCODE_RETC = 63, 134 VGPU10_OPCODE_ROUND_NE = 64, 135 VGPU10_OPCODE_ROUND_NI = 65, 136 VGPU10_OPCODE_ROUND_PI = 66, 137 VGPU10_OPCODE_ROUND_Z = 67, 138 VGPU10_OPCODE_RSQ = 68, 139 VGPU10_OPCODE_SAMPLE = 69, 140 VGPU10_OPCODE_SAMPLE_C = 70, 141 VGPU10_OPCODE_SAMPLE_C_LZ = 71, 142 VGPU10_OPCODE_SAMPLE_L = 72, 143 VGPU10_OPCODE_SAMPLE_D = 73, 144 VGPU10_OPCODE_SAMPLE_B = 74, 145 VGPU10_OPCODE_SQRT = 75, 146 VGPU10_OPCODE_SWITCH = 76, 147 VGPU10_OPCODE_SINCOS = 77, 148 VGPU10_OPCODE_UDIV = 78, 149 VGPU10_OPCODE_ULT = 79, 150 VGPU10_OPCODE_UGE = 80, 151 VGPU10_OPCODE_UMUL = 81, 152 VGPU10_OPCODE_UMAD = 82, 153 VGPU10_OPCODE_UMAX = 83, 154 VGPU10_OPCODE_UMIN = 84, 155 VGPU10_OPCODE_USHR = 85, 156 VGPU10_OPCODE_UTOF = 86, 157 VGPU10_OPCODE_XOR = 87, 158 VGPU10_OPCODE_DCL_RESOURCE = 88, 159 VGPU10_OPCODE_DCL_CONSTANT_BUFFER = 89, 160 VGPU10_OPCODE_DCL_SAMPLER = 90, 161 VGPU10_OPCODE_DCL_INDEX_RANGE = 91, 162 VGPU10_OPCODE_DCL_GS_OUTPUT_PRIMITIVE_TOPOLOGY = 92, 163 VGPU10_OPCODE_DCL_GS_INPUT_PRIMITIVE = 93, 164 VGPU10_OPCODE_DCL_MAX_OUTPUT_VERTEX_COUNT = 94, 165 VGPU10_OPCODE_DCL_INPUT = 95, 166 VGPU10_OPCODE_DCL_INPUT_SGV = 96, 167 VGPU10_OPCODE_DCL_INPUT_SIV = 97, 168 VGPU10_OPCODE_DCL_INPUT_PS = 98, 169 VGPU10_OPCODE_DCL_INPUT_PS_SGV = 99, 170 VGPU10_OPCODE_DCL_INPUT_PS_SIV = 100, 171 VGPU10_OPCODE_DCL_OUTPUT = 101, 172 VGPU10_OPCODE_DCL_OUTPUT_SGV = 102, 173 VGPU10_OPCODE_DCL_OUTPUT_SIV = 103, 174 VGPU10_OPCODE_DCL_TEMPS = 104, 175 VGPU10_OPCODE_DCL_INDEXABLE_TEMP = 105, 176 VGPU10_OPCODE_DCL_GLOBAL_FLAGS = 106, 177 VGPU10_OPCODE_IDIV = 107, 178 VGPU10_NUM_OPCODES /* Should be the last entry. */ 179 } VGPU10_OPCODE_TYPE; 180 181 typedef enum { 182 VGPU10_INTERPOLATION_UNDEFINED = 0, 183 VGPU10_INTERPOLATION_CONSTANT = 1, 184 VGPU10_INTERPOLATION_LINEAR = 2, 185 VGPU10_INTERPOLATION_LINEAR_CENTROID = 3, 186 VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE = 4, 187 VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE_CENTROID = 5, 188 VGPU10_INTERPOLATION_LINEAR_SAMPLE = 6, /* DX10.1 */ 189 VGPU10_INTERPOLATION_LINEAR_NOPERSPECTIVE_SAMPLE = 7 /* DX10.1 */ 190 } VGPU10_INTERPOLATION_MODE; 191 192 typedef enum { 193 VGPU10_RESOURCE_DIMENSION_UNKNOWN = 0, 194 VGPU10_RESOURCE_DIMENSION_BUFFER = 1, 195 VGPU10_RESOURCE_DIMENSION_TEXTURE1D = 2, 196 VGPU10_RESOURCE_DIMENSION_TEXTURE2D = 3, 197 VGPU10_RESOURCE_DIMENSION_TEXTURE2DMS = 4, 198 VGPU10_RESOURCE_DIMENSION_TEXTURE3D = 5, 199 VGPU10_RESOURCE_DIMENSION_TEXTURECUBE = 6, 200 VGPU10_RESOURCE_DIMENSION_TEXTURE1DARRAY = 7, 201 VGPU10_RESOURCE_DIMENSION_TEXTURE2DARRAY = 8, 202 VGPU10_RESOURCE_DIMENSION_TEXTURE2DMSARRAY = 9, 203 VGPU10_RESOURCE_DIMENSION_TEXTURECUBEARRAY = 10 204 } VGPU10_RESOURCE_DIMENSION; 205 206 typedef enum { 207 VGPU10_SAMPLER_MODE_DEFAULT = 0, 208 VGPU10_SAMPLER_MODE_COMPARISON = 1, 209 VGPU10_SAMPLER_MODE_MONO = 2 210 } VGPU10_SAMPLER_MODE; 211 212 typedef enum { 213 VGPU10_INSTRUCTION_TEST_ZERO = 0, 214 VGPU10_INSTRUCTION_TEST_NONZERO = 1 215 } VGPU10_INSTRUCTION_TEST_BOOLEAN; 216 217 typedef enum { 218 VGPU10_CB_IMMEDIATE_INDEXED = 0, 219 VGPU10_CB_DYNAMIC_INDEXED = 1 220 } VGPU10_CB_ACCESS_PATTERN; 221 222 typedef enum { 223 VGPU10_PRIMITIVE_UNDEFINED = 0, 224 VGPU10_PRIMITIVE_POINT = 1, 225 VGPU10_PRIMITIVE_LINE = 2, 226 VGPU10_PRIMITIVE_TRIANGLE = 3, 227 VGPU10_PRIMITIVE_LINE_ADJ = 6, 228 VGPU10_PRIMITIVE_TRIANGLE_ADJ = 7 229 } VGPU10_PRIMITIVE; 230 231 typedef enum { 232 VGPU10_PRIMITIVE_TOPOLOGY_UNDEFINED = 0, 233 VGPU10_PRIMITIVE_TOPOLOGY_POINTLIST = 1, 234 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST = 2, 235 VGPU10_PRIMITIVE_TOPOLOGY_LINESTRIP = 3, 236 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLELIST = 4, 237 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP = 5, 238 VGPU10_PRIMITIVE_TOPOLOGY_LINELIST_ADJ = 10, 239 VGPU10_PRIMITIVE_TOPOLOGY_LINESTRIP_ADJ = 11, 240 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLELIST_ADJ = 12, 241 VGPU10_PRIMITIVE_TOPOLOGY_TRIANGLESTRIP_ADJ = 13 242 } VGPU10_PRIMITIVE_TOPOLOGY; 243 244 typedef enum { 245 VGPU10_CUSTOMDATA_COMMENT = 0, 246 VGPU10_CUSTOMDATA_DEBUGINFO = 1, 247 VGPU10_CUSTOMDATA_OPAQUE = 2, 248 VGPU10_CUSTOMDATA_DCL_IMMEDIATE_CONSTANT_BUFFER = 3 249 } VGPU10_CUSTOMDATA_CLASS; 250 251 typedef enum { 252 VGPU10_RESINFO_RETURN_FLOAT = 0, 253 VGPU10_RESINFO_RETURN_RCPFLOAT = 1, 254 VGPU10_RESINFO_RETURN_UINT = 2 255 } VGPU10_RESINFO_RETURN_TYPE; 256 257 typedef union { 258 struct { 259 unsigned int opcodeType : 11; /* VGPU10_OPCODE_TYPE */ 260 unsigned int interpolationMode : 4; /* VGPU10_INTERPOLATION_MODE */ 261 unsigned int : 3; 262 unsigned int testBoolean : 1; /* VGPU10_INSTRUCTION_TEST_BOOLEAN */ 263 unsigned int : 5; 264 unsigned int instructionLength : 7; 265 unsigned int extended : 1; 266 }; 267 struct { 268 unsigned int : 11; 269 unsigned int resourceDimension : 5; /* VGPU10_RESOURCE_DIMENSION */ 270 }; 271 struct { 272 unsigned int : 11; 273 unsigned int samplerMode : 4; /* VGPU10_SAMPLER_MODE */ 274 }; 275 struct { 276 unsigned int : 11; 277 unsigned int accessPattern : 1; /* VGPU10_CB_ACCESS_PATTERN */ 278 }; 279 struct { 280 unsigned int : 11; 281 unsigned int primitive : 6; /* VGPU10_PRIMITIVE */ 282 }; 283 struct { 284 unsigned int : 11; 285 unsigned int primitiveTopology : 6; /* VGPU10_PRIMITIVE_TOPOLOGY */ 286 }; 287 struct { 288 unsigned int : 11; 289 unsigned int customDataClass : 21; /* VGPU10_CUSTOMDATA_CLASS */ 290 }; 291 struct { 292 unsigned int : 11; 293 unsigned int resinfoReturnType : 2; /* VGPU10_RESINFO_RETURN_TYPE */ 294 unsigned int saturate : 1; 295 }; 296 struct { 297 unsigned int : 11; 298 unsigned int refactoringAllowed : 1; 299 }; 300 uint32 value; 301 } VGPU10OpcodeToken0; 302 303 304 typedef enum { 305 VGPU10_EXTENDED_OPCODE_EMPTY = 0, 306 VGPU10_EXTENDED_OPCODE_SAMPLE_CONTROLS 307 } VGPU10_EXTENDED_OPCODE_TYPE; 308 309 typedef union { 310 struct { 311 unsigned int opcodeType : 6; /* VGPU10_EXTENDED_OPCODE_TYPE */ 312 unsigned int : 3; 313 unsigned int offsetU : 4; /* Two's complement. */ 314 unsigned int offsetV : 4; /* Two's complement. */ 315 unsigned int offsetW : 4; /* Two's complement. */ 316 unsigned int : 10; 317 unsigned int extended : 1; 318 }; 319 uint32 value; 320 } VGPU10OpcodeToken1; 321 322 323 typedef enum { 324 VGPU10_OPERAND_0_COMPONENT = 0, 325 VGPU10_OPERAND_1_COMPONENT = 1, 326 VGPU10_OPERAND_4_COMPONENT = 2, 327 VGPU10_OPERAND_N_COMPONENT = 3 /* Unused for now. */ 328 } VGPU10_OPERAND_NUM_COMPONENTS; 329 330 typedef enum { 331 VGPU10_OPERAND_4_COMPONENT_MASK_MODE = 0, 332 VGPU10_OPERAND_4_COMPONENT_SWIZZLE_MODE = 1, 333 VGPU10_OPERAND_4_COMPONENT_SELECT_1_MODE = 2 334 } VGPU10_OPERAND_4_COMPONENT_SELECTION_MODE; 335 336 #define VGPU10_OPERAND_4_COMPONENT_MASK_X 0x1 337 #define VGPU10_OPERAND_4_COMPONENT_MASK_Y 0x2 338 #define VGPU10_OPERAND_4_COMPONENT_MASK_Z 0x4 339 #define VGPU10_OPERAND_4_COMPONENT_MASK_W 0x8 340 341 #define VGPU10_OPERAND_4_COMPONENT_MASK_XY (VGPU10_OPERAND_4_COMPONENT_MASK_X | VGPU10_OPERAND_4_COMPONENT_MASK_Y) 342 #define VGPU10_OPERAND_4_COMPONENT_MASK_XZ (VGPU10_OPERAND_4_COMPONENT_MASK_X | VGPU10_OPERAND_4_COMPONENT_MASK_Z) 343 #define VGPU10_OPERAND_4_COMPONENT_MASK_XW (VGPU10_OPERAND_4_COMPONENT_MASK_X | VGPU10_OPERAND_4_COMPONENT_MASK_W) 344 #define VGPU10_OPERAND_4_COMPONENT_MASK_YZ (VGPU10_OPERAND_4_COMPONENT_MASK_Y | VGPU10_OPERAND_4_COMPONENT_MASK_Z) 345 #define VGPU10_OPERAND_4_COMPONENT_MASK_YW (VGPU10_OPERAND_4_COMPONENT_MASK_Y | VGPU10_OPERAND_4_COMPONENT_MASK_W) 346 #define VGPU10_OPERAND_4_COMPONENT_MASK_ZW (VGPU10_OPERAND_4_COMPONENT_MASK_Z | VGPU10_OPERAND_4_COMPONENT_MASK_W) 347 #define VGPU10_OPERAND_4_COMPONENT_MASK_XYZ (VGPU10_OPERAND_4_COMPONENT_MASK_XY | VGPU10_OPERAND_4_COMPONENT_MASK_Z) 348 #define VGPU10_OPERAND_4_COMPONENT_MASK_XYW (VGPU10_OPERAND_4_COMPONENT_MASK_XY | VGPU10_OPERAND_4_COMPONENT_MASK_W) 349 #define VGPU10_OPERAND_4_COMPONENT_MASK_XZW (VGPU10_OPERAND_4_COMPONENT_MASK_XZ | VGPU10_OPERAND_4_COMPONENT_MASK_W) 350 #define VGPU10_OPERAND_4_COMPONENT_MASK_YZW (VGPU10_OPERAND_4_COMPONENT_MASK_YZ | VGPU10_OPERAND_4_COMPONENT_MASK_W) 351 #define VGPU10_OPERAND_4_COMPONENT_MASK_XYZW (VGPU10_OPERAND_4_COMPONENT_MASK_XYZ | VGPU10_OPERAND_4_COMPONENT_MASK_W) 352 #define VGPU10_OPERAND_4_COMPONENT_MASK_ALL VGPU10_OPERAND_4_COMPONENT_MASK_XYZW 353 354 #define VGPU10_REGISTER_INDEX_FROM_SEMANTIC 0xffffffff 355 356 typedef enum { 357 VGPU10_COMPONENT_X = 0, 358 VGPU10_COMPONENT_Y = 1, 359 VGPU10_COMPONENT_Z = 2, 360 VGPU10_COMPONENT_W = 3 361 } VGPU10_COMPONENT_NAME; 362 363 typedef enum { 364 VGPU10_OPERAND_TYPE_TEMP = 0, 365 VGPU10_OPERAND_TYPE_INPUT = 1, 366 VGPU10_OPERAND_TYPE_OUTPUT = 2, 367 VGPU10_OPERAND_TYPE_INDEXABLE_TEMP = 3, 368 VGPU10_OPERAND_TYPE_IMMEDIATE32 = 4, 369 VGPU10_OPERAND_TYPE_IMMEDIATE64 = 5, 370 VGPU10_OPERAND_TYPE_SAMPLER = 6, 371 VGPU10_OPERAND_TYPE_RESOURCE = 7, 372 VGPU10_OPERAND_TYPE_CONSTANT_BUFFER = 8, 373 VGPU10_OPERAND_TYPE_IMMEDIATE_CONSTANT_BUFFER = 9, 374 VGPU10_OPERAND_TYPE_LABEL = 10, 375 VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID = 11, 376 VGPU10_OPERAND_TYPE_OUTPUT_DEPTH = 12, 377 VGPU10_OPERAND_TYPE_NULL = 13, 378 VGPU10_OPERAND_TYPE_RASTERIZER = 14, /* DX10.1 */ 379 VGPU10_OPERAND_TYPE_OUTPUT_COVERAGE_MASK = 15 /* DX10.1 */ 380 } VGPU10_OPERAND_TYPE; 381 382 typedef enum { 383 VGPU10_OPERAND_INDEX_0D = 0, 384 VGPU10_OPERAND_INDEX_1D = 1, 385 VGPU10_OPERAND_INDEX_2D = 2, 386 VGPU10_OPERAND_INDEX_3D = 3 387 } VGPU10_OPERAND_INDEX_DIMENSION; 388 389 typedef enum { 390 VGPU10_OPERAND_INDEX_IMMEDIATE32 = 0, 391 VGPU10_OPERAND_INDEX_IMMEDIATE64 = 1, 392 VGPU10_OPERAND_INDEX_RELATIVE = 2, 393 VGPU10_OPERAND_INDEX_IMMEDIATE32_PLUS_RELATIVE = 3, 394 VGPU10_OPERAND_INDEX_IMMEDIATE64_PLUS_RELATIVE = 4 395 } VGPU10_OPERAND_INDEX_REPRESENTATION; 396 397 typedef union { 398 struct { 399 unsigned int numComponents : 2; /* VGPU10_OPERAND_NUM_COMPONENTS */ 400 unsigned int selectionMode : 2; /* VGPU10_OPERAND_4_COMPONENT_SELECTION_MODE */ 401 unsigned int mask : 4; /* D3D10_SB_OPERAND_4_COMPONENT_MASK_* */ 402 unsigned int : 4; 403 unsigned int operandType : 8; /* VGPU10_OPERAND_TYPE */ 404 unsigned int indexDimension : 2; /* VGPU10_OPERAND_INDEX_DIMENSION */ 405 unsigned int index0Representation : 3; /* VGPU10_OPERAND_INDEX_REPRESENTATION */ 406 unsigned int index1Representation : 3; /* VGPU10_OPERAND_INDEX_REPRESENTATION */ 407 unsigned int : 3; 408 unsigned int extended : 1; 409 }; 410 struct { 411 unsigned int : 4; 412 unsigned int swizzleX : 2; /* VGPU10_COMPONENT_NAME */ 413 unsigned int swizzleY : 2; /* VGPU10_COMPONENT_NAME */ 414 unsigned int swizzleZ : 2; /* VGPU10_COMPONENT_NAME */ 415 unsigned int swizzleW : 2; /* VGPU10_COMPONENT_NAME */ 416 }; 417 struct { 418 unsigned int : 4; 419 unsigned int selectMask : 2; /* VGPU10_COMPONENT_NAME */ 420 }; 421 uint32 value; 422 } VGPU10OperandToken0; 423 424 425 typedef enum { 426 VGPU10_EXTENDED_OPERAND_EMPTY = 0, 427 VGPU10_EXTENDED_OPERAND_MODIFIER = 1 428 } VGPU10_EXTENDED_OPERAND_TYPE; 429 430 typedef enum { 431 VGPU10_OPERAND_MODIFIER_NONE = 0, 432 VGPU10_OPERAND_MODIFIER_NEG = 1, 433 VGPU10_OPERAND_MODIFIER_ABS = 2, 434 VGPU10_OPERAND_MODIFIER_ABSNEG = 3 435 } VGPU10_OPERAND_MODIFIER; 436 437 typedef union { 438 struct { 439 unsigned int extendedOperandType : 6; /* VGPU10_EXTENDED_OPERAND_TYPE */ 440 unsigned int operandModifier : 8; /* VGPU10_OPERAND_MODIFIER */ 441 unsigned int : 17; 442 unsigned int extended : 1; 443 }; 444 uint32 value; 445 } VGPU10OperandToken1; 446 447 448 typedef enum { 449 VGPU10_RETURN_TYPE_UNORM = 1, 450 VGPU10_RETURN_TYPE_SNORM = 2, 451 VGPU10_RETURN_TYPE_SINT = 3, 452 VGPU10_RETURN_TYPE_UINT = 4, 453 VGPU10_RETURN_TYPE_FLOAT = 5, 454 VGPU10_RETURN_TYPE_MIXED = 6 455 } VGPU10_RESOURCE_RETURN_TYPE; 456 457 typedef union { 458 struct { 459 unsigned int component0 : 4; /* VGPU10_RESOURCE_RETURN_TYPE */ 460 unsigned int component1 : 4; /* VGPU10_RESOURCE_RETURN_TYPE */ 461 unsigned int component2 : 4; /* VGPU10_RESOURCE_RETURN_TYPE */ 462 unsigned int component3 : 4; /* VGPU10_RESOURCE_RETURN_TYPE */ 463 }; 464 uint32 value; 465 } VGPU10ResourceReturnTypeToken; 466 467 468 typedef enum { 469 VGPU10_NAME_UNDEFINED = 0, 470 VGPU10_NAME_POSITION = 1, 471 VGPU10_NAME_CLIP_DISTANCE = 2, 472 VGPU10_NAME_CULL_DISTANCE = 3, 473 VGPU10_NAME_RENDER_TARGET_ARRAY_INDEX = 4, 474 VGPU10_NAME_VIEWPORT_ARRAY_INDEX = 5, 475 VGPU10_NAME_VERTEX_ID = 6, 476 VGPU10_NAME_PRIMITIVE_ID = 7, 477 VGPU10_NAME_INSTANCE_ID = 8, 478 VGPU10_NAME_IS_FRONT_FACE = 9, 479 VGPU10_NAME_SAMPLE_INDEX = 10, 480 } VGPU10_SYSTEM_NAME; 481 482 typedef union { 483 struct { 484 unsigned int name : 16; /* VGPU10_SYSTEM_NAME */ 485 }; 486 uint32 value; 487 } VGPU10NameToken; 488 489 #endif 490