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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dirtranslator-amdgpu_kernel.ll3 …ernel-arguments=0 -stop-after=irtranslator -global-isel %s -o - | FileCheck -check-prefix=HSA-VI %s
6 ; HSA-VI-LABEL: name: i8_arg
7 ; HSA-VI: bb.1 (%ir-block.0):
8 ; HSA-VI: liveins: $sgpr4_sgpr5
9 ; HSA-VI: [[COPY:%[0-9]+]]:_(p4) = COPY $sgpr4_sgpr5
10 ; HSA-VI: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
11 ; HSA-VI: [[GEP:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C]](s64)
12 …; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `i3…
13 ; HSA-VI: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
14 ; HSA-VI: [[GEP1:%[0-9]+]]:_(p4) = G_GEP [[COPY]], [[C1]](s64)
[all …]
/external/llvm/test/MC/Disassembler/AMDGPU/
Dvop1_vi.txt1 …: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
3 # VI: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
6 # VI: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
9 # VI: v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e]
12 # VI: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
15 # VI: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
18 # VI: v_readfirstlane_b32 s1, v2 ; encoding: [0x02,0x05,0x02,0x7e]
21 # VI: v_cvt_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x07,0x02,0x7e]
24 # VI: v_cvt_f64_i32_e32 v[1:2], v2 ; encoding: [0x02,0x09,0x02,0x7e]
27 # VI: v_cvt_f32_i32_e32 v1, v2 ; encoding: [0x02,0x0b,0x02,0x7e]
[all …]
Dsop1_vi.txt1 …: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
3 # VI: s_mov_b32 s1, s2 ; encoding: [0x02,0x00,0x81,0xbe]
6 # VI: s_mov_b32 s1, 1 ; encoding: [0x81,0x00,0x81,0xbe]
9 # VI: s_mov_b32 s1, 0x64 ; encoding: [0xff,0x00,0x81,0xbe,0x64,0x00,0x00,0x00]
12 # VI: s_mov_b32 s1, 0x80000000 ; encoding: [0xff,0x00,0x81,0xbe,0x00,0x00,0x00,0x80]
15 # VI: s_mov_b32 s0, 0xfe5163ab ; encoding: [0xff,0x00,0x80,0xbe,0xab,0x63,0x51,0xfe]
18 # VI: s_mov_b64 s[2:3], s[4:5] ; encoding: [0x04,0x01,0x82,0xbe]
24 # VI: s_mov_b64 s[2:3], 0xffffffff ; encoding: [0xff,0x01,0x82,0xbe,0xff,0xff,0xff,0xff]
27 # VI: s_mov_b64 s[0:1], 0x80000000 ; encoding: [0xff,0x01,0x80,0xbe,0x00,0x00,0x00,0x80]
30 # VI: s_cmov_b32 s1, 0xc8 ; encoding: [0xff,0x02,0x81,0xbe,0xc8,0x00,0x00,0x00]
[all …]
Dvop2_vi.txt1 …: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
3 # VI: v_cndmask_b32_e32 v1, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x00]
6 # VI: v_readlane_b32 s1, v2, s3 ; encoding: [0x01,0x00,0x89,0xd2,0x02,0x07,0x00,0x00]
9 # VI: v_writelane_b32 v1, s2, s3 ; encoding: [0x01,0x00,0x8a,0xd2,0x02,0x06,0x00,0x00]
12 # VI: v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x02]
15 # VI: v_sub_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x04]
18 # VI: v_subrev_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x06]
21 # VI: v_mul_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x08]
24 # VI: v_mul_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0a]
27 # VI: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0c]
[all …]
Dsop2_vi.txt1 …: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
3 # VI: s_and_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x86]
6 # VI: s_and_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x86]
9 # VI: s_or_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x87]
12 # VI: s_or_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x87]
15 # VI: s_xor_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x88]
18 # VI: s_xor_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x88]
21 # VI: s_andn2_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x89]
24 # VI: s_andn2_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x89]
27 # VI: s_orn2_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x8a]
[all …]
Dds_vi.txt1 …: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
3 # VI: ds_add_u32 v2, v4 offset:16 ; encoding: [0x10,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
6 # VI: ds_write2_b32 v2, v4, v6 offset0:4 ; encoding: [0x04,0x00,0x1c,0xd8,0x02,0x04,0x06,0x00]
9 # VI: ds_write2_b32 v2, v4, v6 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x1c,0xd8,0x02,0x04,0x0…
12 # VI: ds_write2_b32 v2, v4, v6 offset1:8 ; encoding: [0x00,0x08,0x1c,0xd8,0x02,0x04,0x06,0x00]
15 # VI: ds_read2_b32 v[8:9], v2 offset0:4 ; encoding: [0x04,0x00,0x6e,0xd8,0x02,0x00,0x00,0x08]
18 # VI: ds_read2_b32 v[8:9], v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x6e,0xd8,0x02,0x00,0x00…
21 # VI: ds_read2_b32 v[8:9], v2 offset1:8 ; encoding: [0x00,0x08,0x6e,0xd8,0x02,0x00,0x00,0x08]
24 # VI: ds_add_u32 v2, v4 ; encoding: [0x00,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
27 # VI: ds_sub_u32 v2, v4 ; encoding: [0x00,0x00,0x02,0xd8,0x02,0x04,0x00,0x00]
[all …]
Dtrap_vi.txt1 …: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
7 # VI: s_add_u32 ttmp0, ttmp0, 4 ; encoding: [0x70,0x84,0x70,0x80]
10 # VI: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x74,0x74,0x80]
13 # VI: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x74,0xff,0x74,0x80,0x00,0x01,0x00,0x00]
16 # VI: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x74,0x84,0x74,0x80]
19 # VI: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x78,0x74,0x74,0x80]
22 # VI: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x78,0xff,0x7a,0x86,0x80,0x00,0x00,0x00]
25 # VI: s_and_b32 ttmp9, tma_hi, 0xffff ; encoding: [0x6f,0xff,0x79,0x86,0xff,0xff,0x00,0x00]
28 # VI: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x79,0xff,0x79,0x86,0xff,0x01,0x00,0x00]
31 # VI: s_and_b32 ttmp9, tma_lo, 0xffff0000 ; encoding: [0x6e,0xff,0x79,0x86,0x00,0x00,0xff,0xff]
[all …]
Dflat_vi.txt1 …: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
3 # VI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x00,0x01]
6 # VI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x00,0x01]
9 # VI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x00,0x01]
12 # VI: flat_load_dword v1, v[3:4] glc tfe ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x80,0x01]
15 # VI: flat_load_dword v1, v[3:4] glc slc tfe ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x80,0x01]
18 # VI: flat_load_dword v1, v[3:4] slc ; encoding: [0x00,0x00,0x52,0xdc,0x03,0x00,0x00,0x01]
21 # VI: flat_load_dword v1, v[3:4] slc tfe ; encoding: [0x00,0x00,0x52,0xdc,0x03,0x00,0x80,0x01]
24 # VI: flat_load_dword v1, v[3:4] tfe ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x80,0x01]
27 # VI: flat_atomic_add v1, v[3:4], v5 glc slc ; encoding: [0x00,0x00,0x0b,0xdd,0x03,0x05,0x00,0x01]
[all …]
Dvop3_vi.txt1 …: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
3 # VI: v_cmp_lt_f32_e64 s[2:3], v4, -v6 ; encoding: [0x02,0x00,0x41,0xd0,0x04,0x0d,0x02,0x40]
6 # VI: v_cmp_lt_f32_e64 vcc, v4, v6 ; encoding: [0x6a,0x00,0x41,0xd0,0x04,0x0d,0x02,0x00]
9 # VI: v_cmp_lt_f32_e64 s[2:3], -v4, v6 ; encoding: [0x02,0x00,0x41,0xd0,0x04,0x0d,0x02,0x20]
12 # VI: v_cmp_lt_f32_e64 s[2:3], v4, -v6 ; encoding: [0x02,0x00,0x41,0xd0,0x04,0x0d,0x02,0x40]
15 # VI: v_cmp_lt_f32_e64 s[2:3], -v4, -v6 ; encoding: [0x02,0x00,0x41,0xd0,0x04,0x0d,0x02,0x60]
18 # VI: v_cmp_lt_f32_e64 s[2:3], |v4|, v6 ; encoding: [0x02,0x01,0x41,0xd0,0x04,0x0d,0x02,0x00]
21 # VI: v_cmp_lt_f32_e64 s[2:3], v4, |v6| ; encoding: [0x02,0x02,0x41,0xd0,0x04,0x0d,0x02,0x00]
24 # VI: v_cmp_lt_f32_e64 s[2:3], |v4|, |v6| ; encoding: [0x02,0x03,0x41,0xd0,0x04,0x0d,0x02,0x00]
27 # VI: v_cmp_lt_f32_e64 s[2:3], -|v4|, v6 ; encoding: [0x02,0x01,0x41,0xd0,0x04,0x0d,0x02,0x20]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dvop1_vi.txt1 …: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
3 # VI: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
6 # VI: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
9 # VI: v_clrexcp ; encoding: [0x00,0x6a,0x00,0x7e]
12 # VI: v_nop ; encoding: [0x00,0x00,0x00,0x7e]
15 # VI: v_mov_b32_e32 v1, v2 ; encoding: [0x02,0x03,0x02,0x7e]
18 # VI: v_readfirstlane_b32 s1, v2 ; encoding: [0x02,0x05,0x02,0x7e]
21 # VI: v_cvt_i32_f64_e32 v1, v[2:3] ; encoding: [0x02,0x07,0x02,0x7e]
24 # VI: v_cvt_f64_i32_e32 v[1:2], v2 ; encoding: [0x02,0x09,0x02,0x7e]
27 # VI: v_cvt_f32_i32_e32 v1, v2 ; encoding: [0x02,0x0b,0x02,0x7e]
[all …]
Dsop1_vi.txt1 …: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
3 # VI: s_mov_b32 s1, s2 ; encoding: [0x02,0x00,0x81,0xbe]
6 # VI: s_mov_b32 s1, 1 ; encoding: [0x81,0x00,0x81,0xbe]
9 # VI: s_mov_b32 s1, 0x64 ; encoding: [0xff,0x00,0x81,0xbe,0x64,0x00,0x00,0x00]
12 # VI: s_mov_b32 s1, 0x80000000 ; encoding: [0xff,0x00,0x81,0xbe,0x00,0x00,0x00,0x80]
15 # VI: s_mov_b32 s0, 0xfe5163ab ; encoding: [0xff,0x00,0x80,0xbe,0xab,0x63,0x51,0xfe]
18 # VI: s_mov_b32 xnack_mask_lo, -1 ; encoding: [0xc1,0x00,0xe8,0xbe]
21 # VI: s_mov_b32 xnack_mask_hi, -1 ; encoding: [0xc1,0x00,0xe9,0xbe]
24 # VI: s_mov_b64 s[2:3], s[4:5] ; encoding: [0x04,0x01,0x82,0xbe]
27 # VI: s_mov_b64 s[2:3], -1 ; encoding: [0xc1,0x01,0x82,0xbe]
[all …]
Dvop2_vi.txt1 …: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
3 # VI: v_cndmask_b32_e32 v1, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x00]
6 # VI: v_readlane_b32 s1, v2, s3 ; encoding: [0x01,0x00,0x89,0xd2,0x02,0x07,0x00,0x00]
9 # VI: v_writelane_b32 v1, s2, s3 ; encoding: [0x01,0x00,0x8a,0xd2,0x02,0x06,0x00,0x00]
12 # VI: v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x02]
15 # VI: v_sub_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x04]
18 # VI: v_subrev_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x06]
21 # VI: v_mul_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x08]
24 # VI: v_mul_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0a]
27 # VI: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0c]
[all …]
Dsop2_vi.txt1 …: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
3 # VI: s_and_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x86]
6 # VI: s_and_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x86]
9 # VI: s_or_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x87]
12 # VI: s_or_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x87]
15 # VI: s_xor_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x88]
18 # VI: s_xor_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x88]
21 # VI: s_andn2_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x89]
24 # VI: s_andn2_b64 s[2:3], s[4:5], s[6:7] ; encoding: [0x04,0x06,0x82,0x89]
27 # VI: s_orn2_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x8a]
[all …]
Dds_vi.txt1 …: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
3 # VI: ds_add_u32 v2, v4 offset:16 ; encoding: [0x10,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
6 # VI: ds_write2_b32 v2, v4, v6 offset0:4 ; encoding: [0x04,0x00,0x1c,0xd8,0x02,0x04,0x06,0x00]
9 # VI: ds_write2_b32 v2, v4, v6 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x1c,0xd8,0x02,0x04,0x0…
12 # VI: ds_write2_b32 v2, v4, v6 offset1:8 ; encoding: [0x00,0x08,0x1c,0xd8,0x02,0x04,0x06,0x00]
15 # VI: ds_read2_b32 v[8:9], v2 offset0:4 ; encoding: [0x04,0x00,0x6e,0xd8,0x02,0x00,0x00,0x08]
18 # VI: ds_read2_b32 v[8:9], v2 offset0:4 offset1:8 ; encoding: [0x04,0x08,0x6e,0xd8,0x02,0x00,0x00…
21 # VI: ds_read2_b32 v[8:9], v2 offset1:8 ; encoding: [0x00,0x08,0x6e,0xd8,0x02,0x00,0x00,0x08]
24 # VI: ds_add_u32 v2, v4 ; encoding: [0x00,0x00,0x00,0xd8,0x02,0x04,0x00,0x00]
27 # VI: ds_sub_u32 v2, v4 ; encoding: [0x00,0x00,0x02,0xd8,0x02,0x04,0x00,0x00]
[all …]
Dtrap_vi.txt1 …: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
7 # VI: s_add_u32 ttmp0, ttmp0, 4 ; encoding: [0x70,0x84,0x70,0x80]
10 # VI: s_add_u32 ttmp4, 8, ttmp4 ; encoding: [0x88,0x74,0x74,0x80]
13 # VI: s_add_u32 ttmp4, ttmp4, 0x100 ; encoding: [0x74,0xff,0x74,0x80,0x00,0x01,0x00,0x00]
16 # VI: s_add_u32 ttmp4, ttmp4, 4 ; encoding: [0x74,0x84,0x74,0x80]
19 # VI: s_add_u32 ttmp4, ttmp8, ttmp4 ; encoding: [0x78,0x74,0x74,0x80]
22 # VI: s_and_b32 ttmp10, ttmp8, 0x80 ; encoding: [0x78,0xff,0x7a,0x86,0x80,0x00,0x00,0x00]
25 # VI: s_and_b32 ttmp9, tma_hi, 0xffff ; encoding: [0x6f,0xff,0x79,0x86,0xff,0xff,0x00,0x00]
28 # VI: s_and_b32 ttmp9, ttmp9, 0x1ff ; encoding: [0x79,0xff,0x79,0x86,0xff,0x01,0x00,0x00]
31 # VI: s_and_b32 ttmp9, tma_lo, 0xffff0000 ; encoding: [0x6e,0xff,0x79,0x86,0x00,0x00,0xff,0xff]
[all …]
Dflat_vi.txt1 …: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
3 # VI: flat_load_dword v1, v[3:4] ; encoding: [0x00,0x00,0x50,0xdc,0x03,0x00,0x00,0x01]
6 # VI: flat_load_dword v1, v[3:4] glc ; encoding: [0x00,0x00,0x51,0xdc,0x03,0x00,0x00,0x01]
9 # VI: flat_load_dword v1, v[3:4] glc slc ; encoding: [0x00,0x00,0x53,0xdc,0x03,0x00,0x00,0x01]
12 # VI: flat_load_dword v1, v[3:4] slc ; encoding: [0x00,0x00,0x52,0xdc,0x03,0x00,0x00,0x01]
15 # VI: flat_atomic_add v1, v[3:4], v5 glc slc ; encoding: [0x00,0x00,0x0b,0xdd,0x03,0x05,0x00,0x01]
18 # VI: flat_atomic_add v[3:4], v5 slc ; encoding: [0x00,0x00,0x0a,0xdd,0x03,0x05,0x00,0x00]
21 # VI: flat_load_ubyte v1, v[3:4] ; encoding: [0x00,0x00,0x40,0xdc,0x03,0x00,0x00,0x01]
24 # VI: flat_load_sbyte v1, v[3:4] ; encoding: [0x00,0x00,0x44,0xdc,0x03,0x00,0x00,0x01]
27 # VI: flat_load_ushort v1, v[3:4] ; encoding: [0x00,0x00,0x48,0xdc,0x03,0x00,0x00,0x01]
[all …]
Dsopk_vi.txt1 …: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
3 # VI: s_cmovk_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb0]
6 # VI: s_cmpk_eq_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb1]
9 # VI: s_cmpk_lg_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb1]
12 # VI: s_cmpk_gt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb2]
15 # VI: s_cmpk_ge_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb2]
18 # VI: s_cmpk_lt_i32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb3]
21 # VI: s_cmpk_le_i32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb3]
24 # VI: s_cmpk_eq_u32 s2, 0x6 ; encoding: [0x06,0x00,0x02,0xb4]
27 # VI: s_cmpk_lg_u32 s2, 0x6 ; encoding: [0x06,0x00,0x82,0xb4]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Damdgpu-codegenprepare-i16-to-i32.ll2 …le=amdgcn-- -mcpu=tonga -amdgpu-codegenprepare %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
7 ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32
8 ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32
9 ; VI-NEXT: %[[R_32:[0-9]+]] = add nuw nsw i32 %[[A_32]], %[[B_32]]
10 ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3
11 ; VI-NEXT: store volatile i3 %[[R_3]]
21 ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32
22 ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32
23 ; VI-NEXT: %[[R_32:[0-9]+]] = add nuw nsw i32 %[[A_32]], %[[B_32]]
24 ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3
[all …]
Dimmv216.ll2 …-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
124 ; VI-DAG: s_load_dword [[VAL:s[0-9]+]]
125 ; VI-DAG: v_mov_b32_e32 [[CONST0:v[0-9]+]], 0
126 ; VI-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[VAL]], 16
127 ; VI-DAG: v_mov_b32_e32 [[V_SHR:v[0-9]+]], [[SHR]]
129 ; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[V_SHR]], [[CONST0]] dst_sel:WORD_1 dst_unused:UNUSED_PAD sr…
130 ; VI-DAG: v_add_f16_e64 v{{[0-9]+}}, [[VAL]], 0
131 ; VI: v_or_b32
132 ; VI: buffer_store_dword
145 ; VI-DAG: s_load_dword [[VAL:s[0-9]+]]
[all …]
Dkernel-args.ll2 …heck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=VI,GCN,MESA-VI,MESA-GCN,FUNC …
3 …s | FileCheck -allow-deprecated-dag-overlap -enable-var-scope -check-prefixes=VI,GCN,HSA-VI,FUNC %s
8 ; HSA-VI: kernarg_segment_byte_size = 12
9 ; HSA-VI: kernarg_segment_alignment = 4
12 ; MESA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x2c
15 ; HSA-VI: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x8
16 ; HSA-VI: s_and_b32 s{{[0-9]+}}, [[VAL]], 0xff
28 ; HSA-VI: kernarg_segment_byte_size = 12
29 ; HSA-VI: kernarg_segment_alignment = 4
31 ; MESA-VI: s_load_dword s{{[0-9]}}, s[0:1], 0x2c
[all …]
Dllvm.amdgcn.mov.dpp.ll1 …l -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=VI-OPT %s
2 …-verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOOPT %s
6 ; VI-LABEL: {{^}}dpp_test:
7 ; VI: v_mov_b32_e32 v0, s{{[0-9]+}}
8 ; VI-NOOPT: v_mov_b32_e32 v1, s{{[0-9]+}}
9 ; VI-OPT: s_nop 1
10 ; VI-NOOPT: s_nop 0
11 ; VI-NOOPT: s_nop 0
12 ; VI-OPT: v_mov_b32_dpp v0, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 ; encodi…
13 ; VI-NOOPT: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 ; enco…
[all …]
Dflat-scratch-reg.ll2 ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=VI-NOXNACK…
4 …carrizo -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefix=VI-NOXNACK -check-pref…
5 …=stoney -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefix=VI-NOXNACK -check-pref…
7 ; RUN: llc -march=amdgcn -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=VI-XNAC…
8 ; RUN: llc -march=amdgcn -mcpu=stoney -verify-machineinstrs < %s | FileCheck -check-prefix=VI-XNAC…
11 …izo -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefix=HSA-VI-NOXNACK -check-prefi…
12 …izo -mattr=+xnack -verify-machineinstrs < %s | FileCheck -check-prefix=HSA-VI-XNACK -check-prefix=…
16 ; HSA-VI-NOXNACK: is_xnack_enabled = 0
17 ; HSA-VI-XNACK: is_xnack_enabled = 1
20 ; VI-NOXNACK: ; NumSgprs: 8
[all …]
Dimm16.ll1 …mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
8 ; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffff8000{{$}}
25 ; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffff8000{{$}}
42 ; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffffb800{{$}}
59 ; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffffbc00{{$}}
76 ; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffffc000{{$}}
93 ; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffffc400{{$}}
111 ; VI: v_mov_b32_e32 [[REG:v[0-9]+]], 0xffffb118{{$}}
127 ; VI: s_load_dword [[VAL:s[0-9]+]]
128 ; VI: v_add_f16_e64 [[REG:v[0-9]+]], [[VAL]], 0{{$}}
[all …]
Dkernel-argument-dag-lowering.ll1 …ts=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI,GCN,HSA-VI,FUNC %s
8 ; HSA-VI: kernarg_segment_byte_size = 12
9 ; HSA-VI: kernarg_segment_alignment = 4
19 ; HSA-VI: kernarg_segment_byte_size = 12
20 ; HSA-VI: kernarg_segment_alignment = 4
21 ; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x0
22 ; HSA-VI: s_load_dword s{{[0-9]+}}, s[4:5], 0x8
30 ; HSA-VI: kernarg_segment_byte_size = 24
31 ; HSA-VI: kernarg_segment_alignment = 4
32 ; HSA-VI: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[4:5], 0x0
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/AMDGPU/
Dreduction.ll3 …triple=amdgcn-amd-amdhsa -mcpu=fiji -slp-vectorizer -dce < %s | FileCheck -check-prefixes=GCN,VI %s
15 ; VI-LABEL: @reduction_half4(
16 ; VI-NEXT: entry:
17 ; VI-NEXT: [[ELT0:%.*]] = extractelement <4 x half> [[A:%.*]], i64 0
18 ; VI-NEXT: [[ELT1:%.*]] = extractelement <4 x half> [[A]], i64 1
19 ; VI-NEXT: [[ELT2:%.*]] = extractelement <4 x half> [[A]], i64 2
20 ; VI-NEXT: [[ELT3:%.*]] = extractelement <4 x half> [[A]], i64 3
21 ; VI-NEXT: [[ADD1:%.*]] = fadd fast half [[ELT1]], [[ELT0]]
22 ; VI-NEXT: [[ADD2:%.*]] = fadd fast half [[ELT2]], [[ADD1]]
23 ; VI-NEXT: [[ADD3:%.*]] = fadd fast half [[ELT3]], [[ADD2]]
[all …]

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