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1 #ifndef STATE_3D_XML
2 #define STATE_3D_XML
3 
4 /* Autogenerated file, DO NOT EDIT manually!
5 
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
9 
10 The rules-ng-ng source files this header was generated from are:
11 - state.xml     (  26087 bytes, from 2017-10-30 13:44:54)
12 - common.xml    (  26187 bytes, from 2017-10-31 19:05:01)
13 - common_3d.xml (  14615 bytes, from 2017-11-04 14:03:35)
14 - state_hi.xml  (  27733 bytes, from 2017-10-02 19:00:30)
15 - copyright.xml (   1597 bytes, from 2016-10-29 07:29:22)
16 - state_2d.xml  (  51552 bytes, from 2016-10-29 07:29:22)
17 - state_3d.xml  (  79992 bytes, from 2017-11-07 10:44:35)
18 - state_blt.xml (  13405 bytes, from 2017-10-16 17:42:46)
19 - state_vg.xml  (   5975 bytes, from 2016-10-29 07:29:22)
20 
21 Copyright (C) 2012-2017 by the following authors:
22 - Wladimir J. van der Laan <laanwj@gmail.com>
23 - Christian Gmeiner <christian.gmeiner@gmail.com>
24 - Lucas Stach <l.stach@pengutronix.de>
25 - Russell King <rmk@arm.linux.org.uk>
26 
27 Permission is hereby granted, free of charge, to any person obtaining a
28 copy of this software and associated documentation files (the "Software"),
29 to deal in the Software without restriction, including without limitation
30 the rights to use, copy, modify, merge, publish, distribute, sub license,
31 and/or sell copies of the Software, and to permit persons to whom the
32 Software is furnished to do so, subject to the following conditions:
33 
34 The above copyright notice and this permission notice (including the
35 next paragraph) shall be included in all copies or substantial portions
36 of the Software.
37 
38 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
39 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
40 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
41 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
42 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
44 DEALINGS IN THE SOFTWARE.
45 */
46 
47 
48 #define COMPARE_FUNC_NEVER					0x00000000
49 #define COMPARE_FUNC_LESS					0x00000001
50 #define COMPARE_FUNC_EQUAL					0x00000002
51 #define COMPARE_FUNC_LEQUAL					0x00000003
52 #define COMPARE_FUNC_GREATER					0x00000004
53 #define COMPARE_FUNC_NOTEQUAL					0x00000005
54 #define COMPARE_FUNC_GEQUAL					0x00000006
55 #define COMPARE_FUNC_ALWAYS					0x00000007
56 #define STENCIL_OP_KEEP						0x00000000
57 #define STENCIL_OP_ZERO						0x00000001
58 #define STENCIL_OP_REPLACE					0x00000002
59 #define STENCIL_OP_INCR						0x00000003
60 #define STENCIL_OP_DECR						0x00000004
61 #define STENCIL_OP_INVERT					0x00000005
62 #define STENCIL_OP_INCR_WRAP					0x00000006
63 #define STENCIL_OP_DECR_WRAP					0x00000007
64 #define BLEND_EQ_ADD						0x00000000
65 #define BLEND_EQ_SUBTRACT					0x00000001
66 #define BLEND_EQ_REVERSE_SUBTRACT				0x00000002
67 #define BLEND_EQ_MIN						0x00000003
68 #define BLEND_EQ_MAX						0x00000004
69 #define BLEND_FUNC_ZERO						0x00000000
70 #define BLEND_FUNC_ONE						0x00000001
71 #define BLEND_FUNC_SRC_COLOR					0x00000002
72 #define BLEND_FUNC_ONE_MINUS_SRC_COLOR				0x00000003
73 #define BLEND_FUNC_SRC_ALPHA					0x00000004
74 #define BLEND_FUNC_ONE_MINUS_SRC_ALPHA				0x00000005
75 #define BLEND_FUNC_DST_ALPHA					0x00000006
76 #define BLEND_FUNC_ONE_MINUS_DST_ALPHA				0x00000007
77 #define BLEND_FUNC_DST_COLOR					0x00000008
78 #define BLEND_FUNC_ONE_MINUS_DST_COLOR				0x00000009
79 #define BLEND_FUNC_SRC_ALPHA_SATURATE				0x0000000a
80 #define BLEND_FUNC_CONSTANT_ALPHA				0x0000000b
81 #define BLEND_FUNC_ONE_MINUS_CONSTANT_ALPHA			0x0000000c
82 #define BLEND_FUNC_CONSTANT_COLOR				0x0000000d
83 #define BLEND_FUNC_ONE_MINUS_CONSTANT_COLOR			0x0000000e
84 #define RS_FORMAT_X4R4G4B4					0x00000000
85 #define RS_FORMAT_A4R4G4B4					0x00000001
86 #define RS_FORMAT_X1R5G5B5					0x00000002
87 #define RS_FORMAT_A1R5G5B5					0x00000003
88 #define RS_FORMAT_R5G6B5					0x00000004
89 #define RS_FORMAT_X8R8G8B8					0x00000005
90 #define RS_FORMAT_A8R8G8B8					0x00000006
91 #define RS_FORMAT_YUY2						0x00000007
92 #define RS_FORMAT_A8						0x00000010
93 #define RS_FORMAT_R16F						0x00000011
94 #define RS_FORMAT_G16R16F					0x00000012
95 #define RS_FORMAT_A16B16G16R16F					0x00000013
96 #define RS_FORMAT_R32F						0x00000014
97 #define RS_FORMAT_G32R32F					0x00000015
98 #define RS_FORMAT_A2B10G10R10					0x00000016
99 #define RS_FORMAT_R8I						0x00000017
100 #define RS_FORMAT_G8R8I						0x00000018
101 #define RS_FORMAT_A8B8G8R8I					0x00000019
102 #define RS_FORMAT_R16I						0x0000001a
103 #define RS_FORMAT_G16R16I					0x0000001b
104 #define RS_FORMAT_A16B16G16R16I					0x0000001c
105 #define RS_FORMAT_B10G11R11F					0x0000001d
106 #define RS_FORMAT_A2B10G10R10UI					0x0000001e
107 #define RS_FORMAT_G8R8						0x0000001f
108 #define RS_FORMAT_R8						0x00000023
109 #define LOGIC_OP_CLEAR						0x00000000
110 #define LOGIC_OP_NOR						0x00000001
111 #define LOGIC_OP_AND_INVERTED					0x00000002
112 #define LOGIC_OP_COPY_INVERTED					0x00000003
113 #define LOGIC_OP_AND_REVERSE					0x00000004
114 #define LOGIC_OP_INVERT						0x00000005
115 #define LOGIC_OP_XOR						0x00000006
116 #define LOGIC_OP_NAND						0x00000007
117 #define LOGIC_OP_AND						0x00000008
118 #define LOGIC_OP_EQUIV						0x00000009
119 #define LOGIC_OP_NOOP						0x0000000a
120 #define LOGIC_OP_OR_INVERTED					0x0000000b
121 #define LOGIC_OP_COPY						0x0000000c
122 #define LOGIC_OP_OR_REVERSE					0x0000000d
123 #define LOGIC_OP_OR						0x0000000e
124 #define LOGIC_OP_SET						0x0000000f
125 #define TS_SAMPLER_FORMAT_A4R4G4B4				0x00000000
126 #define TS_SAMPLER_FORMAT_A1R5G5B5				0x00000001
127 #define TS_SAMPLER_FORMAT_R5G6B5				0x00000002
128 #define TS_SAMPLER_FORMAT_A8R8G8B8				0x00000003
129 #define TS_SAMPLER_FORMAT_X8R8G8B8				0x00000004
130 #define TS_SAMPLER_FORMAT_D24X8					0x00000005
131 #define TS_SAMPLER_FORMAT_D16					0x00000008
132 #define TS_SAMPLER_FORMAT_RAW					0x0000000f
133 #define VARYING_NUM_COMPONENTS_VAR0__MASK			0x00000007
134 #define VARYING_NUM_COMPONENTS_VAR0__SHIFT			0
135 #define VARYING_NUM_COMPONENTS_VAR0(x)				(((x) << VARYING_NUM_COMPONENTS_VAR0__SHIFT) & VARYING_NUM_COMPONENTS_VAR0__MASK)
136 #define VARYING_NUM_COMPONENTS_VAR1__MASK			0x00000070
137 #define VARYING_NUM_COMPONENTS_VAR1__SHIFT			4
138 #define VARYING_NUM_COMPONENTS_VAR1(x)				(((x) << VARYING_NUM_COMPONENTS_VAR1__SHIFT) & VARYING_NUM_COMPONENTS_VAR1__MASK)
139 #define VARYING_NUM_COMPONENTS_VAR2__MASK			0x00000700
140 #define VARYING_NUM_COMPONENTS_VAR2__SHIFT			8
141 #define VARYING_NUM_COMPONENTS_VAR2(x)				(((x) << VARYING_NUM_COMPONENTS_VAR2__SHIFT) & VARYING_NUM_COMPONENTS_VAR2__MASK)
142 #define VARYING_NUM_COMPONENTS_VAR3__MASK			0x00007000
143 #define VARYING_NUM_COMPONENTS_VAR3__SHIFT			12
144 #define VARYING_NUM_COMPONENTS_VAR3(x)				(((x) << VARYING_NUM_COMPONENTS_VAR3__SHIFT) & VARYING_NUM_COMPONENTS_VAR3__MASK)
145 #define VARYING_NUM_COMPONENTS_VAR4__MASK			0x00070000
146 #define VARYING_NUM_COMPONENTS_VAR4__SHIFT			16
147 #define VARYING_NUM_COMPONENTS_VAR4(x)				(((x) << VARYING_NUM_COMPONENTS_VAR4__SHIFT) & VARYING_NUM_COMPONENTS_VAR4__MASK)
148 #define VARYING_NUM_COMPONENTS_VAR5__MASK			0x00700000
149 #define VARYING_NUM_COMPONENTS_VAR5__SHIFT			20
150 #define VARYING_NUM_COMPONENTS_VAR5(x)				(((x) << VARYING_NUM_COMPONENTS_VAR5__SHIFT) & VARYING_NUM_COMPONENTS_VAR5__MASK)
151 #define VARYING_NUM_COMPONENTS_VAR6__MASK			0x07000000
152 #define VARYING_NUM_COMPONENTS_VAR6__SHIFT			24
153 #define VARYING_NUM_COMPONENTS_VAR6(x)				(((x) << VARYING_NUM_COMPONENTS_VAR6__SHIFT) & VARYING_NUM_COMPONENTS_VAR6__MASK)
154 #define VARYING_NUM_COMPONENTS_VAR7__MASK			0x70000000
155 #define VARYING_NUM_COMPONENTS_VAR7__SHIFT			28
156 #define VARYING_NUM_COMPONENTS_VAR7(x)				(((x) << VARYING_NUM_COMPONENTS_VAR7__SHIFT) & VARYING_NUM_COMPONENTS_VAR7__MASK)
157 #define VIVS_VS							0x00000000
158 
159 #define VIVS_VS_END_PC						0x00000800
160 
161 #define VIVS_VS_OUTPUT_COUNT					0x00000804
162 
163 #define VIVS_VS_INPUT_COUNT					0x00000808
164 #define VIVS_VS_INPUT_COUNT_COUNT__MASK				0x0000000f
165 #define VIVS_VS_INPUT_COUNT_COUNT__SHIFT			0
166 #define VIVS_VS_INPUT_COUNT_COUNT(x)				(((x) << VIVS_VS_INPUT_COUNT_COUNT__SHIFT) & VIVS_VS_INPUT_COUNT_COUNT__MASK)
167 #define VIVS_VS_INPUT_COUNT_UNK8__MASK				0x00001f00
168 #define VIVS_VS_INPUT_COUNT_UNK8__SHIFT				8
169 #define VIVS_VS_INPUT_COUNT_UNK8(x)				(((x) << VIVS_VS_INPUT_COUNT_UNK8__SHIFT) & VIVS_VS_INPUT_COUNT_UNK8__MASK)
170 
171 #define VIVS_VS_TEMP_REGISTER_CONTROL				0x0000080c
172 #define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK		0x0000003f
173 #define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT		0
174 #define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS(x)		(((x) << VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT) & VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK)
175 
176 #define VIVS_VS_OUTPUT(i0)				       (0x00000810 + 0x4*(i0))
177 #define VIVS_VS_OUTPUT__ESIZE					0x00000004
178 #define VIVS_VS_OUTPUT__LEN					0x00000004
179 #define VIVS_VS_OUTPUT_O0__MASK					0x000000ff
180 #define VIVS_VS_OUTPUT_O0__SHIFT				0
181 #define VIVS_VS_OUTPUT_O0(x)					(((x) << VIVS_VS_OUTPUT_O0__SHIFT) & VIVS_VS_OUTPUT_O0__MASK)
182 #define VIVS_VS_OUTPUT_O1__MASK					0x0000ff00
183 #define VIVS_VS_OUTPUT_O1__SHIFT				8
184 #define VIVS_VS_OUTPUT_O1(x)					(((x) << VIVS_VS_OUTPUT_O1__SHIFT) & VIVS_VS_OUTPUT_O1__MASK)
185 #define VIVS_VS_OUTPUT_O2__MASK					0x00ff0000
186 #define VIVS_VS_OUTPUT_O2__SHIFT				16
187 #define VIVS_VS_OUTPUT_O2(x)					(((x) << VIVS_VS_OUTPUT_O2__SHIFT) & VIVS_VS_OUTPUT_O2__MASK)
188 #define VIVS_VS_OUTPUT_O3__MASK					0xff000000
189 #define VIVS_VS_OUTPUT_O3__SHIFT				24
190 #define VIVS_VS_OUTPUT_O3(x)					(((x) << VIVS_VS_OUTPUT_O3__SHIFT) & VIVS_VS_OUTPUT_O3__MASK)
191 
192 #define VIVS_VS_INPUT(i0)				       (0x00000820 + 0x4*(i0))
193 #define VIVS_VS_INPUT__ESIZE					0x00000004
194 #define VIVS_VS_INPUT__LEN					0x00000004
195 #define VIVS_VS_INPUT_I0__MASK					0x000000ff
196 #define VIVS_VS_INPUT_I0__SHIFT					0
197 #define VIVS_VS_INPUT_I0(x)					(((x) << VIVS_VS_INPUT_I0__SHIFT) & VIVS_VS_INPUT_I0__MASK)
198 #define VIVS_VS_INPUT_I1__MASK					0x0000ff00
199 #define VIVS_VS_INPUT_I1__SHIFT					8
200 #define VIVS_VS_INPUT_I1(x)					(((x) << VIVS_VS_INPUT_I1__SHIFT) & VIVS_VS_INPUT_I1__MASK)
201 #define VIVS_VS_INPUT_I2__MASK					0x00ff0000
202 #define VIVS_VS_INPUT_I2__SHIFT					16
203 #define VIVS_VS_INPUT_I2(x)					(((x) << VIVS_VS_INPUT_I2__SHIFT) & VIVS_VS_INPUT_I2__MASK)
204 #define VIVS_VS_INPUT_I3__MASK					0xff000000
205 #define VIVS_VS_INPUT_I3__SHIFT					24
206 #define VIVS_VS_INPUT_I3(x)					(((x) << VIVS_VS_INPUT_I3__SHIFT) & VIVS_VS_INPUT_I3__MASK)
207 
208 #define VIVS_VS_LOAD_BALANCING					0x00000830
209 #define VIVS_VS_LOAD_BALANCING_A__MASK				0x000000ff
210 #define VIVS_VS_LOAD_BALANCING_A__SHIFT				0
211 #define VIVS_VS_LOAD_BALANCING_A(x)				(((x) << VIVS_VS_LOAD_BALANCING_A__SHIFT) & VIVS_VS_LOAD_BALANCING_A__MASK)
212 #define VIVS_VS_LOAD_BALANCING_B__MASK				0x0000ff00
213 #define VIVS_VS_LOAD_BALANCING_B__SHIFT				8
214 #define VIVS_VS_LOAD_BALANCING_B(x)				(((x) << VIVS_VS_LOAD_BALANCING_B__SHIFT) & VIVS_VS_LOAD_BALANCING_B__MASK)
215 #define VIVS_VS_LOAD_BALANCING_C__MASK				0x00ff0000
216 #define VIVS_VS_LOAD_BALANCING_C__SHIFT				16
217 #define VIVS_VS_LOAD_BALANCING_C(x)				(((x) << VIVS_VS_LOAD_BALANCING_C__SHIFT) & VIVS_VS_LOAD_BALANCING_C__MASK)
218 #define VIVS_VS_LOAD_BALANCING_D__MASK				0xff000000
219 #define VIVS_VS_LOAD_BALANCING_D__SHIFT				24
220 #define VIVS_VS_LOAD_BALANCING_D(x)				(((x) << VIVS_VS_LOAD_BALANCING_D__SHIFT) & VIVS_VS_LOAD_BALANCING_D__MASK)
221 
222 #define VIVS_VS_PERF_COUNTER					0x00000834
223 
224 #define VIVS_VS_START_PC					0x00000838
225 
226 #define VIVS_VS_UNK00850					0x00000850
227 
228 #define VIVS_VS_UNK00854					0x00000854
229 
230 #define VIVS_VS_UNK00858					0x00000858
231 
232 #define VIVS_VS_RANGE						0x0000085c
233 #define VIVS_VS_RANGE_LOW__MASK					0x0000ffff
234 #define VIVS_VS_RANGE_LOW__SHIFT				0
235 #define VIVS_VS_RANGE_LOW(x)					(((x) << VIVS_VS_RANGE_LOW__SHIFT) & VIVS_VS_RANGE_LOW__MASK)
236 #define VIVS_VS_RANGE_HIGH__MASK				0xffff0000
237 #define VIVS_VS_RANGE_HIGH__SHIFT				16
238 #define VIVS_VS_RANGE_HIGH(x)					(((x) << VIVS_VS_RANGE_HIGH__SHIFT) & VIVS_VS_RANGE_HIGH__MASK)
239 
240 #define VIVS_VS_UNIFORM_CACHE					0x00000860
241 #define VIVS_VS_UNIFORM_CACHE_FLUSH				0x00000001
242 #define VIVS_VS_UNIFORM_CACHE_PS				0x00000010
243 #define VIVS_VS_UNIFORM_CACHE_RTNE_ROUNDING			0x00001000
244 
245 #define VIVS_VS_UNIFORM_BASE					0x00000864
246 
247 #define VIVS_VS_ICACHE_CONTROL					0x00000868
248 #define VIVS_VS_ICACHE_CONTROL_ENABLE				0x00000001
249 #define VIVS_VS_ICACHE_CONTROL_FLUSH_VS				0x00000010
250 #define VIVS_VS_ICACHE_CONTROL_FLUSH_PS				0x00000020
251 
252 #define VIVS_VS_INST_ADDR					0x0000086c
253 
254 #define VIVS_VS_HALTI5_OUTPUT_COUNT				0x00000870
255 #define VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT__MASK			0x000003ff
256 #define VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT__SHIFT		0
257 #define VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT(x)			(((x) << VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT__SHIFT) & VIVS_VS_HALTI5_OUTPUT_COUNT_COUNT__MASK)
258 #define VIVS_VS_HALTI5_OUTPUT_COUNT_B__MASK			0x0007ff00
259 #define VIVS_VS_HALTI5_OUTPUT_COUNT_B__SHIFT			8
260 #define VIVS_VS_HALTI5_OUTPUT_COUNT_B(x)			(((x) << VIVS_VS_HALTI5_OUTPUT_COUNT_B__SHIFT) & VIVS_VS_HALTI5_OUTPUT_COUNT_B__MASK)
261 
262 #define VIVS_VS_NEWRANGE_LOW					0x00000874
263 
264 #define VIVS_VS_HALTI5_UNK00878					0x00000878
265 
266 #define VIVS_VS_HALTI5_UNK00880					0x00000880
267 
268 #define VIVS_VS_HALTI1_UNK00884					0x00000884
269 
270 #define VIVS_VS_ICACHE_PREFETCH					0x0000088c
271 
272 #define VIVS_VS_ICACHE_UNK00890					0x00000890
273 
274 #define VIVS_VS_HALTI5_UNK00898(i0)			       (0x00000898 + 0x4*(i0))
275 #define VIVS_VS_HALTI5_UNK00898__ESIZE				0x00000004
276 #define VIVS_VS_HALTI5_UNK00898__LEN				0x00000002
277 
278 #define VIVS_VS_HALTI5_UNK008A0					0x000008a0
279 #define VIVS_VS_HALTI5_UNK008A0_A__MASK				0x0000003f
280 #define VIVS_VS_HALTI5_UNK008A0_A__SHIFT			0
281 #define VIVS_VS_HALTI5_UNK008A0_A(x)				(((x) << VIVS_VS_HALTI5_UNK008A0_A__SHIFT) & VIVS_VS_HALTI5_UNK008A0_A__MASK)
282 #define VIVS_VS_HALTI5_UNK008A0_B__MASK				0x0007f000
283 #define VIVS_VS_HALTI5_UNK008A0_B__SHIFT			12
284 #define VIVS_VS_HALTI5_UNK008A0_B(x)				(((x) << VIVS_VS_HALTI5_UNK008A0_B__SHIFT) & VIVS_VS_HALTI5_UNK008A0_B__MASK)
285 #define VIVS_VS_HALTI5_UNK008A0_C__MASK				0x1ff00000
286 #define VIVS_VS_HALTI5_UNK008A0_C__SHIFT			20
287 #define VIVS_VS_HALTI5_UNK008A0_C(x)				(((x) << VIVS_VS_HALTI5_UNK008A0_C__SHIFT) & VIVS_VS_HALTI5_UNK008A0_C__MASK)
288 
289 #define VIVS_VS_SAMPLER_BASE					0x000008a8
290 
291 #define VIVS_VS_ICACHE_INVALIDATE				0x000008b0
292 #define VIVS_VS_ICACHE_INVALIDATE_UNK0				0x00000001
293 #define VIVS_VS_ICACHE_INVALIDATE_UNK1				0x00000002
294 #define VIVS_VS_ICACHE_INVALIDATE_UNK2				0x00000004
295 #define VIVS_VS_ICACHE_INVALIDATE_UNK3				0x00000008
296 #define VIVS_VS_ICACHE_INVALIDATE_UNK4				0x00000010
297 
298 #define VIVS_VS_HALTI5_UNK008B8					0x000008b8
299 
300 #define VIVS_VS_NEWRANGE_HIGH					0x000008bc
301 
302 #define VIVS_VS_HALTI5_INPUT(i0)			       (0x000008c0 + 0x4*(i0))
303 #define VIVS_VS_HALTI5_INPUT__ESIZE				0x00000004
304 #define VIVS_VS_HALTI5_INPUT__LEN				0x00000008
305 #define VIVS_VS_HALTI5_INPUT_I0__MASK				0x000000ff
306 #define VIVS_VS_HALTI5_INPUT_I0__SHIFT				0
307 #define VIVS_VS_HALTI5_INPUT_I0(x)				(((x) << VIVS_VS_HALTI5_INPUT_I0__SHIFT) & VIVS_VS_HALTI5_INPUT_I0__MASK)
308 #define VIVS_VS_HALTI5_INPUT_I1__MASK				0x0000ff00
309 #define VIVS_VS_HALTI5_INPUT_I1__SHIFT				8
310 #define VIVS_VS_HALTI5_INPUT_I1(x)				(((x) << VIVS_VS_HALTI5_INPUT_I1__SHIFT) & VIVS_VS_HALTI5_INPUT_I1__MASK)
311 #define VIVS_VS_HALTI5_INPUT_I2__MASK				0x00ff0000
312 #define VIVS_VS_HALTI5_INPUT_I2__SHIFT				16
313 #define VIVS_VS_HALTI5_INPUT_I2(x)				(((x) << VIVS_VS_HALTI5_INPUT_I2__SHIFT) & VIVS_VS_HALTI5_INPUT_I2__MASK)
314 #define VIVS_VS_HALTI5_INPUT_I3__MASK				0xff000000
315 #define VIVS_VS_HALTI5_INPUT_I3__SHIFT				24
316 #define VIVS_VS_HALTI5_INPUT_I3(x)				(((x) << VIVS_VS_HALTI5_INPUT_I3__SHIFT) & VIVS_VS_HALTI5_INPUT_I3__MASK)
317 
318 #define VIVS_VS_HALTI5_OUTPUT(i0)			       (0x000008e0 + 0x4*(i0))
319 #define VIVS_VS_HALTI5_OUTPUT__ESIZE				0x00000004
320 #define VIVS_VS_HALTI5_OUTPUT__LEN				0x00000008
321 #define VIVS_VS_HALTI5_OUTPUT_O0__MASK				0x000000ff
322 #define VIVS_VS_HALTI5_OUTPUT_O0__SHIFT				0
323 #define VIVS_VS_HALTI5_OUTPUT_O0(x)				(((x) << VIVS_VS_HALTI5_OUTPUT_O0__SHIFT) & VIVS_VS_HALTI5_OUTPUT_O0__MASK)
324 #define VIVS_VS_HALTI5_OUTPUT_O1__MASK				0x0000ff00
325 #define VIVS_VS_HALTI5_OUTPUT_O1__SHIFT				8
326 #define VIVS_VS_HALTI5_OUTPUT_O1(x)				(((x) << VIVS_VS_HALTI5_OUTPUT_O1__SHIFT) & VIVS_VS_HALTI5_OUTPUT_O1__MASK)
327 #define VIVS_VS_HALTI5_OUTPUT_O2__MASK				0x00ff0000
328 #define VIVS_VS_HALTI5_OUTPUT_O2__SHIFT				16
329 #define VIVS_VS_HALTI5_OUTPUT_O2(x)				(((x) << VIVS_VS_HALTI5_OUTPUT_O2__SHIFT) & VIVS_VS_HALTI5_OUTPUT_O2__MASK)
330 #define VIVS_VS_HALTI5_OUTPUT_O3__MASK				0xff000000
331 #define VIVS_VS_HALTI5_OUTPUT_O3__SHIFT				24
332 #define VIVS_VS_HALTI5_OUTPUT_O3(x)				(((x) << VIVS_VS_HALTI5_OUTPUT_O3__SHIFT) & VIVS_VS_HALTI5_OUTPUT_O3__MASK)
333 
334 #define VIVS_VS_INST_MEM(i0)				       (0x00004000 + 0x4*(i0))
335 #define VIVS_VS_INST_MEM__ESIZE					0x00000004
336 #define VIVS_VS_INST_MEM__LEN					0x00000400
337 
338 #define VIVS_VS_UNIFORMS(i0)				       (0x00005000 + 0x4*(i0))
339 #define VIVS_VS_UNIFORMS__ESIZE					0x00000004
340 #define VIVS_VS_UNIFORMS__LEN					0x00000400
341 
342 #define VIVS_VS_ICACHE_COUNT					0x00015604
343 
344 #define VIVS_CL							0x00000000
345 
346 #define VIVS_CL_CONFIG						0x00000900
347 #define VIVS_CL_CONFIG_DIMENSIONS__MASK				0x00000003
348 #define VIVS_CL_CONFIG_DIMENSIONS__SHIFT			0
349 #define VIVS_CL_CONFIG_DIMENSIONS(x)				(((x) << VIVS_CL_CONFIG_DIMENSIONS__SHIFT) & VIVS_CL_CONFIG_DIMENSIONS__MASK)
350 #define VIVS_CL_CONFIG_TRAVERSE_ORDER__MASK			0x00000070
351 #define VIVS_CL_CONFIG_TRAVERSE_ORDER__SHIFT			4
352 #define VIVS_CL_CONFIG_TRAVERSE_ORDER(x)			(((x) << VIVS_CL_CONFIG_TRAVERSE_ORDER__SHIFT) & VIVS_CL_CONFIG_TRAVERSE_ORDER__MASK)
353 #define VIVS_CL_CONFIG_ENABLE_SWATH_X				0x00000100
354 #define VIVS_CL_CONFIG_ENABLE_SWATH_Y				0x00000200
355 #define VIVS_CL_CONFIG_ENABLE_SWATH_Z				0x00000400
356 #define VIVS_CL_CONFIG_SWATH_SIZE_X__MASK			0x0000f000
357 #define VIVS_CL_CONFIG_SWATH_SIZE_X__SHIFT			12
358 #define VIVS_CL_CONFIG_SWATH_SIZE_X(x)				(((x) << VIVS_CL_CONFIG_SWATH_SIZE_X__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_X__MASK)
359 #define VIVS_CL_CONFIG_SWATH_SIZE_Y__MASK			0x000f0000
360 #define VIVS_CL_CONFIG_SWATH_SIZE_Y__SHIFT			16
361 #define VIVS_CL_CONFIG_SWATH_SIZE_Y(x)				(((x) << VIVS_CL_CONFIG_SWATH_SIZE_Y__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_Y__MASK)
362 #define VIVS_CL_CONFIG_SWATH_SIZE_Z__MASK			0x00f00000
363 #define VIVS_CL_CONFIG_SWATH_SIZE_Z__SHIFT			20
364 #define VIVS_CL_CONFIG_SWATH_SIZE_Z(x)				(((x) << VIVS_CL_CONFIG_SWATH_SIZE_Z__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_Z__MASK)
365 #define VIVS_CL_CONFIG_VALUE_ORDER__MASK			0x07000000
366 #define VIVS_CL_CONFIG_VALUE_ORDER__SHIFT			24
367 #define VIVS_CL_CONFIG_VALUE_ORDER(x)				(((x) << VIVS_CL_CONFIG_VALUE_ORDER__SHIFT) & VIVS_CL_CONFIG_VALUE_ORDER__MASK)
368 
369 #define VIVS_CL_GLOBAL_X					0x00000904
370 #define VIVS_CL_GLOBAL_X_SIZE__MASK				0x0000ffff
371 #define VIVS_CL_GLOBAL_X_SIZE__SHIFT				0
372 #define VIVS_CL_GLOBAL_X_SIZE(x)				(((x) << VIVS_CL_GLOBAL_X_SIZE__SHIFT) & VIVS_CL_GLOBAL_X_SIZE__MASK)
373 #define VIVS_CL_GLOBAL_X_OFFSET__MASK				0xffff0000
374 #define VIVS_CL_GLOBAL_X_OFFSET__SHIFT				16
375 #define VIVS_CL_GLOBAL_X_OFFSET(x)				(((x) << VIVS_CL_GLOBAL_X_OFFSET__SHIFT) & VIVS_CL_GLOBAL_X_OFFSET__MASK)
376 
377 #define VIVS_CL_GLOBAL_Y					0x00000908
378 #define VIVS_CL_GLOBAL_Y_SIZE__MASK				0x0000ffff
379 #define VIVS_CL_GLOBAL_Y_SIZE__SHIFT				0
380 #define VIVS_CL_GLOBAL_Y_SIZE(x)				(((x) << VIVS_CL_GLOBAL_Y_SIZE__SHIFT) & VIVS_CL_GLOBAL_Y_SIZE__MASK)
381 #define VIVS_CL_GLOBAL_Y_OFFSET__MASK				0xffff0000
382 #define VIVS_CL_GLOBAL_Y_OFFSET__SHIFT				16
383 #define VIVS_CL_GLOBAL_Y_OFFSET(x)				(((x) << VIVS_CL_GLOBAL_Y_OFFSET__SHIFT) & VIVS_CL_GLOBAL_Y_OFFSET__MASK)
384 
385 #define VIVS_CL_GLOBAL_Z					0x0000090c
386 #define VIVS_CL_GLOBAL_Z_SIZE__MASK				0x0000ffff
387 #define VIVS_CL_GLOBAL_Z_SIZE__SHIFT				0
388 #define VIVS_CL_GLOBAL_Z_SIZE(x)				(((x) << VIVS_CL_GLOBAL_Z_SIZE__SHIFT) & VIVS_CL_GLOBAL_Z_SIZE__MASK)
389 #define VIVS_CL_GLOBAL_Z_OFFSET__MASK				0xffff0000
390 #define VIVS_CL_GLOBAL_Z_OFFSET__SHIFT				16
391 #define VIVS_CL_GLOBAL_Z_OFFSET(x)				(((x) << VIVS_CL_GLOBAL_Z_OFFSET__SHIFT) & VIVS_CL_GLOBAL_Z_OFFSET__MASK)
392 
393 #define VIVS_CL_WORKGROUP_X					0x00000910
394 #define VIVS_CL_WORKGROUP_X_SIZE__MASK				0x000003ff
395 #define VIVS_CL_WORKGROUP_X_SIZE__SHIFT				0
396 #define VIVS_CL_WORKGROUP_X_SIZE(x)				(((x) << VIVS_CL_WORKGROUP_X_SIZE__SHIFT) & VIVS_CL_WORKGROUP_X_SIZE__MASK)
397 #define VIVS_CL_WORKGROUP_X_COUNT__MASK				0xffff0000
398 #define VIVS_CL_WORKGROUP_X_COUNT__SHIFT			16
399 #define VIVS_CL_WORKGROUP_X_COUNT(x)				(((x) << VIVS_CL_WORKGROUP_X_COUNT__SHIFT) & VIVS_CL_WORKGROUP_X_COUNT__MASK)
400 
401 #define VIVS_CL_WORKGROUP_Y					0x00000914
402 #define VIVS_CL_WORKGROUP_Y_SIZE__MASK				0x000003ff
403 #define VIVS_CL_WORKGROUP_Y_SIZE__SHIFT				0
404 #define VIVS_CL_WORKGROUP_Y_SIZE(x)				(((x) << VIVS_CL_WORKGROUP_Y_SIZE__SHIFT) & VIVS_CL_WORKGROUP_Y_SIZE__MASK)
405 #define VIVS_CL_WORKGROUP_Y_COUNT__MASK				0xffff0000
406 #define VIVS_CL_WORKGROUP_Y_COUNT__SHIFT			16
407 #define VIVS_CL_WORKGROUP_Y_COUNT(x)				(((x) << VIVS_CL_WORKGROUP_Y_COUNT__SHIFT) & VIVS_CL_WORKGROUP_Y_COUNT__MASK)
408 
409 #define VIVS_CL_WORKGROUP_Z					0x00000918
410 #define VIVS_CL_WORKGROUP_Z_SIZE__MASK				0x000003ff
411 #define VIVS_CL_WORKGROUP_Z_SIZE__SHIFT				0
412 #define VIVS_CL_WORKGROUP_Z_SIZE(x)				(((x) << VIVS_CL_WORKGROUP_Z_SIZE__SHIFT) & VIVS_CL_WORKGROUP_Z_SIZE__MASK)
413 #define VIVS_CL_WORKGROUP_Z_COUNT__MASK				0xffff0000
414 #define VIVS_CL_WORKGROUP_Z_COUNT__SHIFT			16
415 #define VIVS_CL_WORKGROUP_Z_COUNT(x)				(((x) << VIVS_CL_WORKGROUP_Z_COUNT__SHIFT) & VIVS_CL_WORKGROUP_Z_COUNT__MASK)
416 
417 #define VIVS_CL_THREAD_ALLOCATION				0x0000091c
418 
419 #define VIVS_CL_KICKER						0x00000920
420 
421 #define VIVS_CL_UNK00924					0x00000924
422 
423 #define VIVS_CL_UNK00940					0x00000940
424 
425 #define VIVS_CL_UNK00944					0x00000944
426 
427 #define VIVS_CL_UNK00948					0x00000948
428 
429 #define VIVS_CL_UNK0094C					0x0000094c
430 
431 #define VIVS_CL_UNK00950					0x00000950
432 
433 #define VIVS_CL_UNK00954					0x00000954
434 
435 #define VIVS_CL_HALTI5_UNK00958					0x00000958
436 
437 #define VIVS_CL_HALTI5_UNK0095C					0x0000095c
438 
439 #define VIVS_CL_HALTI5_UNK00960					0x00000960
440 
441 #define VIVS_PA							0x00000000
442 
443 #define VIVS_PA_VIEWPORT_SCALE_X				0x00000a00
444 
445 #define VIVS_PA_VIEWPORT_SCALE_Y				0x00000a04
446 
447 #define VIVS_PA_VIEWPORT_SCALE_Z				0x00000a08
448 
449 #define VIVS_PA_VIEWPORT_OFFSET_X				0x00000a0c
450 
451 #define VIVS_PA_VIEWPORT_OFFSET_Y				0x00000a10
452 
453 #define VIVS_PA_VIEWPORT_OFFSET_Z				0x00000a14
454 
455 #define VIVS_PA_LINE_WIDTH					0x00000a18
456 
457 #define VIVS_PA_POINT_SIZE					0x00000a1c
458 
459 #define VIVS_PA_UNK00A24					0x00000a24
460 
461 #define VIVS_PA_SYSTEM_MODE					0x00000a28
462 #define VIVS_PA_SYSTEM_MODE_PROVOKING_VERTEX_LAST		0x00000001
463 #define VIVS_PA_SYSTEM_MODE_HALF_PIXEL_CENTER			0x00000010
464 
465 #define VIVS_PA_W_CLIP_LIMIT					0x00000a2c
466 
467 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT				0x00000a30
468 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__MASK		0x000000ff
469 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__SHIFT		0
470 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0(x)			(((x) << VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__SHIFT) & VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__MASK)
471 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__MASK		0x0000ff00
472 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__SHIFT		8
473 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT(x)		(((x) << VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__SHIFT) & VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__MASK)
474 
475 #define VIVS_PA_CONFIG						0x00000a34
476 #define VIVS_PA_CONFIG_POINT_SIZE_ENABLE			0x00000004
477 #define VIVS_PA_CONFIG_POINT_SIZE_ENABLE_MASK			0x00000008
478 #define VIVS_PA_CONFIG_POINT_SPRITE_ENABLE			0x00000010
479 #define VIVS_PA_CONFIG_POINT_SPRITE_ENABLE_MASK			0x00000020
480 #define VIVS_PA_CONFIG_CULL_FACE_MODE__MASK			0x00000300
481 #define VIVS_PA_CONFIG_CULL_FACE_MODE__SHIFT			8
482 #define VIVS_PA_CONFIG_CULL_FACE_MODE_OFF			0x00000000
483 #define VIVS_PA_CONFIG_CULL_FACE_MODE_CW			0x00000100
484 #define VIVS_PA_CONFIG_CULL_FACE_MODE_CCW			0x00000200
485 #define VIVS_PA_CONFIG_CULL_FACE_MODE_MASK			0x00000400
486 #define VIVS_PA_CONFIG_FILL_MODE__MASK				0x00003000
487 #define VIVS_PA_CONFIG_FILL_MODE__SHIFT				12
488 #define VIVS_PA_CONFIG_FILL_MODE_POINT				0x00000000
489 #define VIVS_PA_CONFIG_FILL_MODE_WIREFRAME			0x00001000
490 #define VIVS_PA_CONFIG_FILL_MODE_SOLID				0x00002000
491 #define VIVS_PA_CONFIG_FILL_MODE_MASK				0x00004000
492 #define VIVS_PA_CONFIG_SHADE_MODEL__MASK			0x00030000
493 #define VIVS_PA_CONFIG_SHADE_MODEL__SHIFT			16
494 #define VIVS_PA_CONFIG_SHADE_MODEL_FLAT				0x00000000
495 #define VIVS_PA_CONFIG_SHADE_MODEL_SMOOTH			0x00010000
496 #define VIVS_PA_CONFIG_SHADE_MODEL_MASK				0x00040000
497 #define VIVS_PA_CONFIG_WIDE_LINE				0x00400000
498 #define VIVS_PA_CONFIG_WIDE_LINE_MASK				0x00800000
499 
500 #define VIVS_PA_WIDE_LINE_WIDTH0				0x00000a38
501 
502 #define VIVS_PA_WIDE_LINE_WIDTH1				0x00000a3c
503 
504 #define VIVS_PA_SHADER_ATTRIBUTES(i0)			       (0x00000a40 + 0x4*(i0))
505 #define VIVS_PA_SHADER_ATTRIBUTES__ESIZE			0x00000004
506 #define VIVS_PA_SHADER_ATTRIBUTES__LEN				0x0000000a
507 #define VIVS_PA_SHADER_ATTRIBUTES_BYPASS_FLAT			0x00000001
508 #define VIVS_PA_SHADER_ATTRIBUTES_UNK4__MASK			0x000000f0
509 #define VIVS_PA_SHADER_ATTRIBUTES_UNK4__SHIFT			4
510 #define VIVS_PA_SHADER_ATTRIBUTES_UNK4(x)			(((x) << VIVS_PA_SHADER_ATTRIBUTES_UNK4__SHIFT) & VIVS_PA_SHADER_ATTRIBUTES_UNK4__MASK)
511 #define VIVS_PA_SHADER_ATTRIBUTES_UNK8__MASK			0x00000f00
512 #define VIVS_PA_SHADER_ATTRIBUTES_UNK8__SHIFT			8
513 #define VIVS_PA_SHADER_ATTRIBUTES_UNK8(x)			(((x) << VIVS_PA_SHADER_ATTRIBUTES_UNK8__SHIFT) & VIVS_PA_SHADER_ATTRIBUTES_UNK8__MASK)
514 
515 #define VIVS_PA_VIEWPORT_UNK00A80				0x00000a80
516 
517 #define VIVS_PA_VIEWPORT_UNK00A84				0x00000a84
518 
519 #define VIVS_PA_FLAGS						0x00000a88
520 #define VIVS_PA_FLAGS_UNK24					0x01000000
521 #define VIVS_PA_FLAGS_ZCONVERT_BYPASS				0x40000000
522 
523 #define VIVS_PA_ZFARCLIPPING					0x00000a8c
524 
525 #define VIVS_PA_VARYING_NUM_COMPONENTS(i0)		       (0x00000a90 + 0x4*(i0))
526 #define VIVS_PA_VARYING_NUM_COMPONENTS__ESIZE			0x00000004
527 #define VIVS_PA_VARYING_NUM_COMPONENTS__LEN			0x00000004
528 
529 #define VIVS_PA_VS_OUTPUT_COUNT					0x00000aa8
530 
531 #define VIVS_SE							0x00000000
532 
533 #define VIVS_SE_SCISSOR_LEFT					0x00000c00
534 
535 #define VIVS_SE_SCISSOR_TOP					0x00000c04
536 
537 #define VIVS_SE_SCISSOR_RIGHT					0x00000c08
538 
539 #define VIVS_SE_SCISSOR_BOTTOM					0x00000c0c
540 
541 #define VIVS_SE_DEPTH_SCALE					0x00000c10
542 
543 #define VIVS_SE_DEPTH_BIAS					0x00000c14
544 
545 #define VIVS_SE_CONFIG						0x00000c18
546 #define VIVS_SE_CONFIG_LAST_PIXEL_ENABLE			0x00000001
547 
548 #define VIVS_SE_UNK00C1C					0x00000c1c
549 
550 #define VIVS_SE_CLIP_RIGHT					0x00000c20
551 
552 #define VIVS_SE_CLIP_BOTTOM					0x00000c24
553 
554 #define VIVS_RA							0x00000000
555 
556 #define VIVS_RA_CONTROL						0x00000e00
557 #define VIVS_RA_CONTROL_UNK0					0x00000001
558 #define VIVS_RA_CONTROL_LAST_VARYING_2X				0x00000002
559 
560 #define VIVS_RA_MULTISAMPLE_UNK00E04				0x00000e04
561 
562 #define VIVS_RA_EARLY_DEPTH					0x00000e08
563 
564 #define VIVS_RA_UNK00E0C					0x00000e0c
565 
566 #define VIVS_RA_MULTISAMPLE_UNK00E10(i0)		       (0x00000e10 + 0x4*(i0))
567 #define VIVS_RA_MULTISAMPLE_UNK00E10__ESIZE			0x00000004
568 #define VIVS_RA_MULTISAMPLE_UNK00E10__LEN			0x00000004
569 
570 #define VIVS_RA_HDEPTH_CONTROL					0x00000e20
571 #define VIVS_RA_HDEPTH_CONTROL_UNK0				0x00000001
572 #define VIVS_RA_HDEPTH_CONTROL_COMPARE__MASK			0x00007000
573 #define VIVS_RA_HDEPTH_CONTROL_COMPARE__SHIFT			12
574 #define VIVS_RA_HDEPTH_CONTROL_COMPARE(x)			(((x) << VIVS_RA_HDEPTH_CONTROL_COMPARE__SHIFT) & VIVS_RA_HDEPTH_CONTROL_COMPARE__MASK)
575 
576 #define VIVS_RA_UNK00E24					0x00000e24
577 
578 #define VIVS_RA_HALTI5_UNK00E34					0x00000e34
579 
580 #define VIVS_RA_CENTROID_TABLE(i0)			       (0x00000e40 + 0x4*(i0))
581 #define VIVS_RA_CENTROID_TABLE__ESIZE				0x00000004
582 #define VIVS_RA_CENTROID_TABLE__LEN				0x00000010
583 
584 #define VIVS_PS							0x00000000
585 
586 #define VIVS_PS_END_PC						0x00001000
587 
588 #define VIVS_PS_OUTPUT_REG					0x00001004
589 
590 #define VIVS_PS_INPUT_COUNT					0x00001008
591 #define VIVS_PS_INPUT_COUNT_COUNT__MASK				0x0000000f
592 #define VIVS_PS_INPUT_COUNT_COUNT__SHIFT			0
593 #define VIVS_PS_INPUT_COUNT_COUNT(x)				(((x) << VIVS_PS_INPUT_COUNT_COUNT__SHIFT) & VIVS_PS_INPUT_COUNT_COUNT__MASK)
594 #define VIVS_PS_INPUT_COUNT_UNK8__MASK				0x00001f00
595 #define VIVS_PS_INPUT_COUNT_UNK8__SHIFT				8
596 #define VIVS_PS_INPUT_COUNT_UNK8(x)				(((x) << VIVS_PS_INPUT_COUNT_UNK8__SHIFT) & VIVS_PS_INPUT_COUNT_UNK8__MASK)
597 #define VIVS_PS_INPUT_COUNT_DUAL16				0x00010000
598 
599 #define VIVS_PS_TEMP_REGISTER_CONTROL				0x0000100c
600 #define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK		0x0000003f
601 #define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT		0
602 #define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS(x)		(((x) << VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT) & VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK)
603 
604 #define VIVS_PS_CONTROL						0x00001010
605 #define VIVS_PS_CONTROL_BYPASS					0x00000001
606 #define VIVS_PS_CONTROL_UNK1					0x00000002
607 
608 #define VIVS_PS_PERF_COUNTER					0x00001014
609 
610 #define VIVS_PS_START_PC					0x00001018
611 
612 #define VIVS_PS_RANGE						0x0000101c
613 #define VIVS_PS_RANGE_LOW__MASK					0x0000ffff
614 #define VIVS_PS_RANGE_LOW__SHIFT				0
615 #define VIVS_PS_RANGE_LOW(x)					(((x) << VIVS_PS_RANGE_LOW__SHIFT) & VIVS_PS_RANGE_LOW__MASK)
616 #define VIVS_PS_RANGE_HIGH__MASK				0xffff0000
617 #define VIVS_PS_RANGE_HIGH__SHIFT				16
618 #define VIVS_PS_RANGE_HIGH(x)					(((x) << VIVS_PS_RANGE_HIGH__SHIFT) & VIVS_PS_RANGE_HIGH__MASK)
619 
620 #define VIVS_PS_UNIFORM_BASE					0x00001024
621 
622 #define VIVS_PS_INST_ADDR					0x00001028
623 
624 #define VIVS_PS_UNK0102C					0x0000102c
625 
626 #define VIVS_PS_CONTROL_EXT					0x00001030
627 #define VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT__MASK		0x00000003
628 #define VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT__SHIFT		0
629 #define VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT(x)		(((x) << VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT__SHIFT) & VIVS_PS_CONTROL_EXT_COLOR_OUTPUT_COUNT__MASK)
630 
631 #define VIVS_PS_UNK01034					0x00001034
632 
633 #define VIVS_PS_UNK01038					0x00001038
634 
635 #define VIVS_PS_HALTI3_UNK0103C					0x0000103c
636 
637 #define VIVS_PS_UNK01040(i0)				       (0x00001040 + 0x4*(i0))
638 #define VIVS_PS_UNK01040__ESIZE					0x00000004
639 #define VIVS_PS_UNK01040__LEN					0x00000002
640 
641 #define VIVS_PS_ICACHE_PREFETCH					0x00001048
642 
643 #define VIVS_PS_ICACHE_UNK0104C					0x0000104c
644 
645 #define VIVS_PS_MSAA_CONFIG					0x00001054
646 
647 #define VIVS_PS_SAMPLER_BASE					0x00001058
648 
649 #define VIVS_PS_VARYING_NUM_COMPONENTS(i0)		       (0x00001080 + 0x4*(i0))
650 #define VIVS_PS_VARYING_NUM_COMPONENTS__ESIZE			0x00000004
651 #define VIVS_PS_VARYING_NUM_COMPONENTS__LEN			0x00000004
652 
653 #define VIVS_PS_NEWRANGE_LOW					0x0000087c
654 
655 #define VIVS_PS_NEWRANGE_HIGH					0x00001090
656 
657 #define VIVS_PS_ICACHE_COUNT					0x00001094
658 
659 #define VIVS_PS_HALTI5_UNK01098					0x00001098
660 
661 #define VIVS_PS_INST_MEM(i0)				       (0x00006000 + 0x4*(i0))
662 #define VIVS_PS_INST_MEM__ESIZE					0x00000004
663 #define VIVS_PS_INST_MEM__LEN					0x00000400
664 
665 #define VIVS_PS_UNIFORMS(i0)				       (0x00007000 + 0x4*(i0))
666 #define VIVS_PS_UNIFORMS__ESIZE					0x00000004
667 #define VIVS_PS_UNIFORMS__LEN					0x00000400
668 
669 #define VIVS_GS							0x00000000
670 
671 #define VIVS_GS_UNK01100					0x00001100
672 
673 #define VIVS_GS_UNK01104					0x00001104
674 
675 #define VIVS_GS_UNK01108					0x00001108
676 
677 #define VIVS_GS_UNK0110C					0x0000110c
678 
679 #define VIVS_GS_UNK01110					0x00001110
680 
681 #define VIVS_GS_UNK01114					0x00001114
682 
683 #define VIVS_GS_ICACHE_PREFETCH					0x00001118
684 
685 #define VIVS_GS_UNK0111C					0x0000111c
686 
687 #define VIVS_GS_UNK01120(i0)				       (0x00001120 + 0x4*(i0))
688 #define VIVS_GS_UNK01120__ESIZE					0x00000004
689 #define VIVS_GS_UNK01120__LEN					0x00000008
690 
691 #define VIVS_GS_UNK01140					0x00001140
692 
693 #define VIVS_GS_UNK01144					0x00001144
694 
695 #define VIVS_GS_UNK01148					0x00001148
696 
697 #define VIVS_GS_UNK0114C					0x0000114c
698 
699 #define VIVS_GS_UNK01154					0x00001154
700 
701 #define VIVS_TCS						0x00000000
702 
703 #define VIVS_TCS_UNK007C0					0x000007c0
704 
705 #define VIVS_TCS_UNK14A00					0x00014a00
706 
707 #define VIVS_TCS_UNK14A04					0x00014a04
708 
709 #define VIVS_TCS_UNK14A08					0x00014a08
710 
711 #define VIVS_TCS_ICACHE_PREFETCH				0x00014a0c
712 
713 #define VIVS_TCS_UNK14A10					0x00014a10
714 
715 #define VIVS_TCS_UNK14A14					0x00014a14
716 
717 #define VIVS_TCS_UNK14A18					0x00014a18
718 
719 #define VIVS_TCS_UNK14A1C					0x00014a1c
720 
721 #define VIVS_TCS_UNK14A20(i0)				       (0x00014a20 + 0x4*(i0))
722 #define VIVS_TCS_UNK14A20__ESIZE				0x00000004
723 #define VIVS_TCS_UNK14A20__LEN					0x00000008
724 
725 #define VIVS_TCS_UNK14A40					0x00014a40
726 
727 #define VIVS_TCS_UNK14A44					0x00014a44
728 
729 #define VIVS_TCS_UNK14A4C					0x00014a4c
730 
731 #define VIVS_TES						0x00000000
732 
733 #define VIVS_TES_UNK14B00					0x00014b00
734 
735 #define VIVS_TES_UNK14B04					0x00014b04
736 
737 #define VIVS_TES_UNK14B08					0x00014b08
738 
739 #define VIVS_TES_UNK14B0C					0x00014b0c
740 
741 #define VIVS_TES_ICACHE_PREFETCH				0x00014b10
742 
743 #define VIVS_TES_UNK14B14					0x00014b14
744 
745 #define VIVS_TES_UNK14B18					0x00014b18
746 
747 #define VIVS_TES_UNK14B1C					0x00014b1c
748 
749 #define VIVS_TES_UNK14B20					0x00014b20
750 
751 #define VIVS_TES_UNK14B24					0x00014b24
752 
753 #define VIVS_TES_UNK14B2C					0x00014b2c
754 
755 #define VIVS_TES_UNK14B34					0x00014b34
756 
757 #define VIVS_TES_UNK14B40(i0)				       (0x00014b40 + 0x4*(i0))
758 #define VIVS_TES_UNK14B40__ESIZE				0x00000004
759 #define VIVS_TES_UNK14B40__LEN					0x00000008
760 
761 #define VIVS_TFB						0x00000000
762 
763 #define VIVS_TFB_UNK1C000					0x0001c000
764 
765 #define VIVS_TFB_UNK1C008					0x0001c008
766 
767 #define VIVS_TFB_FLUSH						0x0001c00c
768 
769 #define VIVS_TFB_UNK1C014					0x0001c014
770 
771 #define VIVS_TFB_UNK1C040(i0)				       (0x0001c040 + 0x4*(i0))
772 #define VIVS_TFB_UNK1C040__ESIZE				0x00000004
773 #define VIVS_TFB_UNK1C040__LEN					0x00000004
774 
775 #define VIVS_TFB_UNK1C080(i0)				       (0x0001c080 + 0x4*(i0))
776 #define VIVS_TFB_UNK1C080__ESIZE				0x00000004
777 #define VIVS_TFB_UNK1C080__LEN					0x00000004
778 
779 #define VIVS_TFB_UNK1C0C0(i0)				       (0x0001c0c0 + 0x4*(i0))
780 #define VIVS_TFB_UNK1C0C0__ESIZE				0x00000004
781 #define VIVS_TFB_UNK1C0C0__LEN					0x00000004
782 
783 #define VIVS_TFB_UNK1C100(i0)				       (0x0001c100 + 0x4*(i0))
784 #define VIVS_TFB_UNK1C100__ESIZE				0x00000004
785 #define VIVS_TFB_UNK1C100__LEN					0x00000004
786 
787 #define VIVS_TFB_UNK1C800(i0)				       (0x0001c800 + 0x4*(i0))
788 #define VIVS_TFB_UNK1C800__ESIZE				0x00000004
789 #define VIVS_TFB_UNK1C800__LEN					0x00000200
790 
791 #define VIVS_PE							0x00000000
792 
793 #define VIVS_PE_DEPTH_CONFIG					0x00001400
794 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE__MASK			0x00000003
795 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE__SHIFT			0
796 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE			0x00000000
797 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z			0x00000001
798 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_W			0x00000002
799 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_MASK			0x00000008
800 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT__MASK			0x00000010
801 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT__SHIFT		4
802 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16			0x00000000
803 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D24S8			0x00000010
804 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_MASK			0x00000020
805 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__MASK			0x00000700
806 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__SHIFT			8
807 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC(x)			(((x) << VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__SHIFT) & VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__MASK)
808 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC_MASK			0x00000800
809 #define VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE			0x00001000
810 #define VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE_MASK			0x00002000
811 #define VIVS_PE_DEPTH_CONFIG_EARLY_Z				0x00010000
812 #define VIVS_PE_DEPTH_CONFIG_EARLY_Z_MASK			0x00020000
813 #define VIVS_PE_DEPTH_CONFIG_UNK18				0x00040000
814 #define VIVS_PE_DEPTH_CONFIG_UNK18_MASK				0x00080000
815 #define VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH				0x00100000
816 #define VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH_MASK			0x00200000
817 #define VIVS_PE_DEPTH_CONFIG_DISABLE_ZS				0x01000000
818 #define VIVS_PE_DEPTH_CONFIG_DISABLE_ZS_MASK			0x02000000
819 #define VIVS_PE_DEPTH_CONFIG_SUPER_TILED			0x04000000
820 #define VIVS_PE_DEPTH_CONFIG_SUPER_TILED_MASK			0x08000000
821 
822 #define VIVS_PE_DEPTH_NEAR					0x00001404
823 
824 #define VIVS_PE_DEPTH_FAR					0x00001408
825 
826 #define VIVS_PE_DEPTH_NORMALIZE					0x0000140c
827 
828 #define VIVS_PE_DEPTH_ADDR					0x00001410
829 
830 #define VIVS_PE_DEPTH_STRIDE					0x00001414
831 
832 #define VIVS_PE_STENCIL_OP					0x00001418
833 #define VIVS_PE_STENCIL_OP_FUNC_FRONT__MASK			0x00000007
834 #define VIVS_PE_STENCIL_OP_FUNC_FRONT__SHIFT			0
835 #define VIVS_PE_STENCIL_OP_FUNC_FRONT(x)			(((x) << VIVS_PE_STENCIL_OP_FUNC_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_FUNC_FRONT__MASK)
836 #define VIVS_PE_STENCIL_OP_FUNC_FRONT_MASK			0x00000008
837 #define VIVS_PE_STENCIL_OP_PASS_FRONT__MASK			0x00000070
838 #define VIVS_PE_STENCIL_OP_PASS_FRONT__SHIFT			4
839 #define VIVS_PE_STENCIL_OP_PASS_FRONT(x)			(((x) << VIVS_PE_STENCIL_OP_PASS_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_PASS_FRONT__MASK)
840 #define VIVS_PE_STENCIL_OP_PASS_FRONT_MASK			0x00000080
841 #define VIVS_PE_STENCIL_OP_FAIL_FRONT__MASK			0x00000700
842 #define VIVS_PE_STENCIL_OP_FAIL_FRONT__SHIFT			8
843 #define VIVS_PE_STENCIL_OP_FAIL_FRONT(x)			(((x) << VIVS_PE_STENCIL_OP_FAIL_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_FAIL_FRONT__MASK)
844 #define VIVS_PE_STENCIL_OP_FAIL_FRONT_MASK			0x00000800
845 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__MASK		0x00007000
846 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__SHIFT		12
847 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT(x)			(((x) << VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__MASK)
848 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT_MASK		0x00008000
849 #define VIVS_PE_STENCIL_OP_FUNC_BACK__MASK			0x00070000
850 #define VIVS_PE_STENCIL_OP_FUNC_BACK__SHIFT			16
851 #define VIVS_PE_STENCIL_OP_FUNC_BACK(x)				(((x) << VIVS_PE_STENCIL_OP_FUNC_BACK__SHIFT) & VIVS_PE_STENCIL_OP_FUNC_BACK__MASK)
852 #define VIVS_PE_STENCIL_OP_FUNC_BACK_MASK			0x00080000
853 #define VIVS_PE_STENCIL_OP_PASS_BACK__MASK			0x00700000
854 #define VIVS_PE_STENCIL_OP_PASS_BACK__SHIFT			20
855 #define VIVS_PE_STENCIL_OP_PASS_BACK(x)				(((x) << VIVS_PE_STENCIL_OP_PASS_BACK__SHIFT) & VIVS_PE_STENCIL_OP_PASS_BACK__MASK)
856 #define VIVS_PE_STENCIL_OP_PASS_BACK_MASK			0x00800000
857 #define VIVS_PE_STENCIL_OP_FAIL_BACK__MASK			0x07000000
858 #define VIVS_PE_STENCIL_OP_FAIL_BACK__SHIFT			24
859 #define VIVS_PE_STENCIL_OP_FAIL_BACK(x)				(((x) << VIVS_PE_STENCIL_OP_FAIL_BACK__SHIFT) & VIVS_PE_STENCIL_OP_FAIL_BACK__MASK)
860 #define VIVS_PE_STENCIL_OP_FAIL_BACK_MASK			0x08000000
861 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__MASK		0x70000000
862 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__SHIFT		28
863 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK(x)			(((x) << VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__SHIFT) & VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__MASK)
864 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK_MASK			0x80000000
865 
866 #define VIVS_PE_STENCIL_CONFIG					0x0000141c
867 #define VIVS_PE_STENCIL_CONFIG_MODE__MASK			0x00000003
868 #define VIVS_PE_STENCIL_CONFIG_MODE__SHIFT			0
869 #define VIVS_PE_STENCIL_CONFIG_MODE_DISABLED			0x00000000
870 #define VIVS_PE_STENCIL_CONFIG_MODE_ONE_SIDED			0x00000001
871 #define VIVS_PE_STENCIL_CONFIG_MODE_TWO_SIDED			0x00000002
872 #define VIVS_PE_STENCIL_CONFIG_MODE_MASK			0x00000010
873 #define VIVS_PE_STENCIL_CONFIG_REF_FRONT_MASK			0x00000020
874 #define VIVS_PE_STENCIL_CONFIG_MASK_FRONT_MASK			0x00000040
875 #define VIVS_PE_STENCIL_CONFIG_WRITE_MASK_MASK			0x00000080
876 #define VIVS_PE_STENCIL_CONFIG_REF_FRONT__MASK			0x0000ff00
877 #define VIVS_PE_STENCIL_CONFIG_REF_FRONT__SHIFT			8
878 #define VIVS_PE_STENCIL_CONFIG_REF_FRONT(x)			(((x) << VIVS_PE_STENCIL_CONFIG_REF_FRONT__SHIFT) & VIVS_PE_STENCIL_CONFIG_REF_FRONT__MASK)
879 #define VIVS_PE_STENCIL_CONFIG_MASK_FRONT__MASK			0x00ff0000
880 #define VIVS_PE_STENCIL_CONFIG_MASK_FRONT__SHIFT		16
881 #define VIVS_PE_STENCIL_CONFIG_MASK_FRONT(x)			(((x) << VIVS_PE_STENCIL_CONFIG_MASK_FRONT__SHIFT) & VIVS_PE_STENCIL_CONFIG_MASK_FRONT__MASK)
882 #define VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT__MASK		0xff000000
883 #define VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT__SHIFT		24
884 #define VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT(x)		(((x) << VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT__SHIFT) & VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT__MASK)
885 
886 #define VIVS_PE_ALPHA_OP					0x00001420
887 #define VIVS_PE_ALPHA_OP_ALPHA_TEST				0x00000001
888 #define VIVS_PE_ALPHA_OP_ALPHA_TEST_MASK			0x00000002
889 #define VIVS_PE_ALPHA_OP_ALPHA_FUNC__MASK			0x00000070
890 #define VIVS_PE_ALPHA_OP_ALPHA_FUNC__SHIFT			4
891 #define VIVS_PE_ALPHA_OP_ALPHA_FUNC(x)				(((x) << VIVS_PE_ALPHA_OP_ALPHA_FUNC__SHIFT) & VIVS_PE_ALPHA_OP_ALPHA_FUNC__MASK)
892 #define VIVS_PE_ALPHA_OP_ALPHA_FUNC_MASK			0x00000080
893 #define VIVS_PE_ALPHA_OP_ALPHA_REF__MASK			0x0000ff00
894 #define VIVS_PE_ALPHA_OP_ALPHA_REF__SHIFT			8
895 #define VIVS_PE_ALPHA_OP_ALPHA_REF(x)				(((x) << VIVS_PE_ALPHA_OP_ALPHA_REF__SHIFT) & VIVS_PE_ALPHA_OP_ALPHA_REF__MASK)
896 #define VIVS_PE_ALPHA_OP_ALPHA_REF_MASKFUNC_MASK		0x00010000
897 
898 #define VIVS_PE_ALPHA_BLEND_COLOR				0x00001424
899 #define VIVS_PE_ALPHA_BLEND_COLOR_B__MASK			0x000000ff
900 #define VIVS_PE_ALPHA_BLEND_COLOR_B__SHIFT			0
901 #define VIVS_PE_ALPHA_BLEND_COLOR_B(x)				(((x) << VIVS_PE_ALPHA_BLEND_COLOR_B__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_B__MASK)
902 #define VIVS_PE_ALPHA_BLEND_COLOR_G__MASK			0x0000ff00
903 #define VIVS_PE_ALPHA_BLEND_COLOR_G__SHIFT			8
904 #define VIVS_PE_ALPHA_BLEND_COLOR_G(x)				(((x) << VIVS_PE_ALPHA_BLEND_COLOR_G__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_G__MASK)
905 #define VIVS_PE_ALPHA_BLEND_COLOR_R__MASK			0x00ff0000
906 #define VIVS_PE_ALPHA_BLEND_COLOR_R__SHIFT			16
907 #define VIVS_PE_ALPHA_BLEND_COLOR_R(x)				(((x) << VIVS_PE_ALPHA_BLEND_COLOR_R__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_R__MASK)
908 #define VIVS_PE_ALPHA_BLEND_COLOR_A__MASK			0xff000000
909 #define VIVS_PE_ALPHA_BLEND_COLOR_A__SHIFT			24
910 #define VIVS_PE_ALPHA_BLEND_COLOR_A(x)				(((x) << VIVS_PE_ALPHA_BLEND_COLOR_A__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_A__MASK)
911 
912 #define VIVS_PE_ALPHA_CONFIG					0x00001428
913 #define VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR			0x00000001
914 #define VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR_MASK		0x00000002
915 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR_MASK		0x00000004
916 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR_MASK		0x00000008
917 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__MASK		0x000000f0
918 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__SHIFT		4
919 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR(x)			(((x) << VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__SHIFT) & VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__MASK)
920 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__MASK		0x00000f00
921 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__SHIFT		8
922 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR(x)			(((x) << VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__SHIFT) & VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__MASK)
923 #define VIVS_PE_ALPHA_CONFIG_EQ_COLOR__MASK			0x00007000
924 #define VIVS_PE_ALPHA_CONFIG_EQ_COLOR__SHIFT			12
925 #define VIVS_PE_ALPHA_CONFIG_EQ_COLOR(x)			(((x) << VIVS_PE_ALPHA_CONFIG_EQ_COLOR__SHIFT) & VIVS_PE_ALPHA_CONFIG_EQ_COLOR__MASK)
926 #define VIVS_PE_ALPHA_CONFIG_EQ_COLOR_MASK			0x00008000
927 #define VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA		0x00010000
928 #define VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA_MASK		0x00020000
929 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA_MASK		0x00040000
930 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA_MASK		0x00080000
931 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__MASK		0x00f00000
932 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__SHIFT		20
933 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA(x)			(((x) << VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__SHIFT) & VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__MASK)
934 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__MASK		0x0f000000
935 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__SHIFT		24
936 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA(x)			(((x) << VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__SHIFT) & VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__MASK)
937 #define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__MASK			0x70000000
938 #define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__SHIFT			28
939 #define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA(x)			(((x) << VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__SHIFT) & VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__MASK)
940 #define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA_MASK			0x80000000
941 
942 #define VIVS_PE_COLOR_FORMAT					0x0000142c
943 #define VIVS_PE_COLOR_FORMAT_FORMAT__MASK			0x0000000f
944 #define VIVS_PE_COLOR_FORMAT_FORMAT__SHIFT			0
945 #define VIVS_PE_COLOR_FORMAT_FORMAT(x)				(((x) << VIVS_PE_COLOR_FORMAT_FORMAT__SHIFT) & VIVS_PE_COLOR_FORMAT_FORMAT__MASK)
946 #define VIVS_PE_COLOR_FORMAT_FORMAT_MASK			0x00000010
947 #define VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK			0x00000f00
948 #define VIVS_PE_COLOR_FORMAT_COMPONENTS__SHIFT			8
949 #define VIVS_PE_COLOR_FORMAT_COMPONENTS(x)			(((x) << VIVS_PE_COLOR_FORMAT_COMPONENTS__SHIFT) & VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK)
950 #define VIVS_PE_COLOR_FORMAT_SUPER_TILED_NEW			0x00002000
951 #define VIVS_PE_COLOR_FORMAT_COMPONENTS_MASK			0x00001000
952 #define VIVS_PE_COLOR_FORMAT_OVERWRITE				0x00010000
953 #define VIVS_PE_COLOR_FORMAT_OVERWRITE_MASK			0x00020000
954 #define VIVS_PE_COLOR_FORMAT_SUPER_TILED			0x00100000
955 #define VIVS_PE_COLOR_FORMAT_SUPER_TILED_MASK			0x00200000
956 #define VIVS_PE_COLOR_FORMAT_FORMAT_EXT__MASK			0x7f000000
957 #define VIVS_PE_COLOR_FORMAT_FORMAT_EXT__SHIFT			24
958 #define VIVS_PE_COLOR_FORMAT_FORMAT_EXT(x)			(((x) << VIVS_PE_COLOR_FORMAT_FORMAT_EXT__SHIFT) & VIVS_PE_COLOR_FORMAT_FORMAT_EXT__MASK)
959 #define VIVS_PE_COLOR_FORMAT_FORMAT_EXT_MASK			0x80000000
960 
961 #define VIVS_PE_COLOR_ADDR					0x00001430
962 
963 #define VIVS_PE_COLOR_STRIDE					0x00001434
964 
965 #define VIVS_PE_HDEPTH_CONTROL					0x00001454
966 #define VIVS_PE_HDEPTH_CONTROL_FORMAT__MASK			0x0000000f
967 #define VIVS_PE_HDEPTH_CONTROL_FORMAT__SHIFT			0
968 #define VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED			0x00000000
969 #define VIVS_PE_HDEPTH_CONTROL_FORMAT_D16			0x00000005
970 #define VIVS_PE_HDEPTH_CONTROL_FORMAT_D24S8			0x00000008
971 
972 #define VIVS_PE_HDEPTH_ADDR					0x00001458
973 
974 #define VIVS_PE_UNK0145C					0x0000145c
975 
976 #define VIVS_PE_PIPE(i0)				       (0x00000000 + 0x4*(i0))
977 #define VIVS_PE_PIPE__ESIZE					0x00000004
978 #define VIVS_PE_PIPE__LEN					0x00000008
979 
980 #define VIVS_PE_PIPE_COLOR_ADDR(i0)			       (0x00001460 + 0x4*(i0))
981 
982 #define VIVS_PE_PIPE_DEPTH_ADDR(i0)			       (0x00001480 + 0x4*(i0))
983 
984 #define VIVS_PE_PIPE_ADDR_UNK01500(i0)			       (0x00001500 + 0x4*(i0))
985 
986 #define VIVS_PE_PIPE_ADDR_UNK01520(i0)			       (0x00001520 + 0x4*(i0))
987 
988 #define VIVS_PE_PIPE_ADDR_UNK01540(i0)			       (0x00001540 + 0x4*(i0))
989 
990 #define VIVS_PE_STENCIL_CONFIG_EXT				0x000014a0
991 #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__MASK		0x000000ff
992 #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__SHIFT		0
993 #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(x)			(((x) << VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__MASK)
994 #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK_MASK		0x00000100
995 #define VIVS_PE_STENCIL_CONFIG_EXT_UNK16_MASK			0x00000200
996 #define VIVS_PE_STENCIL_CONFIG_EXT_UNK16__MASK			0xffff0000
997 #define VIVS_PE_STENCIL_CONFIG_EXT_UNK16__SHIFT			16
998 #define VIVS_PE_STENCIL_CONFIG_EXT_UNK16(x)			(((x) << VIVS_PE_STENCIL_CONFIG_EXT_UNK16__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT_UNK16__MASK)
999 
1000 #define VIVS_PE_LOGIC_OP					0x000014a4
1001 #define VIVS_PE_LOGIC_OP_OP__MASK				0x0000000f
1002 #define VIVS_PE_LOGIC_OP_OP__SHIFT				0
1003 #define VIVS_PE_LOGIC_OP_OP(x)					(((x) << VIVS_PE_LOGIC_OP_OP__SHIFT) & VIVS_PE_LOGIC_OP_OP__MASK)
1004 #define VIVS_PE_LOGIC_OP_OP_MASK				0x00000010
1005 #define VIVS_PE_LOGIC_OP_SINGLE_BUFFER_MASK			0x00000080
1006 #define VIVS_PE_LOGIC_OP_SINGLE_BUFFER__MASK			0x00000300
1007 #define VIVS_PE_LOGIC_OP_SINGLE_BUFFER__SHIFT			8
1008 #define VIVS_PE_LOGIC_OP_SINGLE_BUFFER(x)			(((x) << VIVS_PE_LOGIC_OP_SINGLE_BUFFER__SHIFT) & VIVS_PE_LOGIC_OP_SINGLE_BUFFER__MASK)
1009 #define VIVS_PE_LOGIC_OP_UNK11_MASK				0x00000400
1010 #define VIVS_PE_LOGIC_OP_UNK11					0x00000800
1011 #define VIVS_PE_LOGIC_OP_UNK20__MASK				0x00300000
1012 #define VIVS_PE_LOGIC_OP_UNK20__SHIFT				20
1013 #define VIVS_PE_LOGIC_OP_UNK20(x)				(((x) << VIVS_PE_LOGIC_OP_UNK20__SHIFT) & VIVS_PE_LOGIC_OP_UNK20__MASK)
1014 #define VIVS_PE_LOGIC_OP_UNK20_MASK				0x00800000
1015 #define VIVS_PE_LOGIC_OP_UNK24__MASK				0x07000000
1016 #define VIVS_PE_LOGIC_OP_UNK24__SHIFT				24
1017 #define VIVS_PE_LOGIC_OP_UNK24(x)				(((x) << VIVS_PE_LOGIC_OP_UNK24__SHIFT) & VIVS_PE_LOGIC_OP_UNK24__MASK)
1018 #define VIVS_PE_LOGIC_OP_UNK24_MASK				0x08000000
1019 #define VIVS_PE_LOGIC_OP_UNK31_MASK				0x40000000
1020 #define VIVS_PE_LOGIC_OP_UNK31					0x80000000
1021 
1022 #define VIVS_PE_DITHER(i0)				       (0x000014a8 + 0x4*(i0))
1023 #define VIVS_PE_DITHER__ESIZE					0x00000004
1024 #define VIVS_PE_DITHER__LEN					0x00000002
1025 
1026 #define VIVS_PE_ALPHA_COLOR_EXT0				0x000014b0
1027 #define VIVS_PE_ALPHA_COLOR_EXT0_B__MASK			0x0000ffff
1028 #define VIVS_PE_ALPHA_COLOR_EXT0_B__SHIFT			0
1029 #define VIVS_PE_ALPHA_COLOR_EXT0_B(x)				(((x) << VIVS_PE_ALPHA_COLOR_EXT0_B__SHIFT) & VIVS_PE_ALPHA_COLOR_EXT0_B__MASK)
1030 #define VIVS_PE_ALPHA_COLOR_EXT0_G__MASK			0xffff0000
1031 #define VIVS_PE_ALPHA_COLOR_EXT0_G__SHIFT			16
1032 #define VIVS_PE_ALPHA_COLOR_EXT0_G(x)				(((x) << VIVS_PE_ALPHA_COLOR_EXT0_G__SHIFT) & VIVS_PE_ALPHA_COLOR_EXT0_G__MASK)
1033 
1034 #define VIVS_PE_ALPHA_COLOR_EXT1				0x000014b4
1035 #define VIVS_PE_ALPHA_COLOR_EXT1_R__MASK			0x0000ffff
1036 #define VIVS_PE_ALPHA_COLOR_EXT1_R__SHIFT			0
1037 #define VIVS_PE_ALPHA_COLOR_EXT1_R(x)				(((x) << VIVS_PE_ALPHA_COLOR_EXT1_R__SHIFT) & VIVS_PE_ALPHA_COLOR_EXT1_R__MASK)
1038 #define VIVS_PE_ALPHA_COLOR_EXT1_A__MASK			0xffff0000
1039 #define VIVS_PE_ALPHA_COLOR_EXT1_A__SHIFT			16
1040 #define VIVS_PE_ALPHA_COLOR_EXT1_A(x)				(((x) << VIVS_PE_ALPHA_COLOR_EXT1_A__SHIFT) & VIVS_PE_ALPHA_COLOR_EXT1_A__MASK)
1041 
1042 #define VIVS_PE_STENCIL_CONFIG_EXT2				0x000014b8
1043 #define VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK__MASK		0x000000ff
1044 #define VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK__SHIFT		0
1045 #define VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK(x)		(((x) << VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK__MASK)
1046 #define VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__MASK	0x0000ff00
1047 #define VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__SHIFT	8
1048 #define VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK(x)		(((x) << VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__MASK)
1049 
1050 #define VIVS_PE_MEM_CONFIG					0x000014bc
1051 #define VIVS_PE_MEM_CONFIG_COLOR_CACHE_MODE__MASK		0x01000000
1052 #define VIVS_PE_MEM_CONFIG_COLOR_CACHE_MODE__SHIFT		24
1053 #define VIVS_PE_MEM_CONFIG_COLOR_CACHE_MODE(x)			(((x) << VIVS_PE_MEM_CONFIG_COLOR_CACHE_MODE__SHIFT) & VIVS_PE_MEM_CONFIG_COLOR_CACHE_MODE__MASK)
1054 #define VIVS_PE_MEM_CONFIG_DEPTH_CACHE_MODE__MASK		0x04000000
1055 #define VIVS_PE_MEM_CONFIG_DEPTH_CACHE_MODE__SHIFT		26
1056 #define VIVS_PE_MEM_CONFIG_DEPTH_CACHE_MODE(x)			(((x) << VIVS_PE_MEM_CONFIG_DEPTH_CACHE_MODE__SHIFT) & VIVS_PE_MEM_CONFIG_DEPTH_CACHE_MODE__MASK)
1057 
1058 #define VIVS_PE_HALTI4_UNK014C0					0x000014c0
1059 
1060 #define VIVS_PE_ROBUSTNESS_UNK014C4				0x000014c4
1061 
1062 #define VIVS_PE_UNK01580(i0)				       (0x00001580 + 0x4*(i0))
1063 #define VIVS_PE_UNK01580__ESIZE					0x00000004
1064 #define VIVS_PE_UNK01580__LEN					0x00000003
1065 
1066 #define VIVS_PE_RT_ADDR(i0)				       (0x00000000 + 0x20*(i0))
1067 #define VIVS_PE_RT_ADDR__ESIZE					0x00000020
1068 #define VIVS_PE_RT_ADDR__LEN					0x00000008
1069 
1070 #define VIVS_PE_RT_ADDR_PIPE(i0, i1)			       (0x00014800 + 0x20*(i0) + 0x4*(i1))
1071 #define VIVS_PE_RT_ADDR_PIPE__ESIZE				0x00000004
1072 #define VIVS_PE_RT_ADDR_PIPE__LEN				0x00000008
1073 
1074 #define VIVS_PE_RT_CONFIG(i0)				       (0x00014900 + 0x4*(i0))
1075 #define VIVS_PE_RT_CONFIG__ESIZE				0x00000004
1076 #define VIVS_PE_RT_CONFIG__LEN					0x00000008
1077 #define VIVS_PE_RT_CONFIG_STRIDE__MASK				0x0000ffff
1078 #define VIVS_PE_RT_CONFIG_STRIDE__SHIFT				0
1079 #define VIVS_PE_RT_CONFIG_STRIDE(x)				(((x) << VIVS_PE_RT_CONFIG_STRIDE__SHIFT) & VIVS_PE_RT_CONFIG_STRIDE__MASK)
1080 #define VIVS_PE_RT_CONFIG_UNK16__MASK				0xffff0000
1081 #define VIVS_PE_RT_CONFIG_UNK16__SHIFT				16
1082 #define VIVS_PE_RT_CONFIG_UNK16(x)				(((x) << VIVS_PE_RT_CONFIG_UNK16__SHIFT) & VIVS_PE_RT_CONFIG_UNK16__MASK)
1083 
1084 #define VIVS_PE_HALTI5_UNK14920(i0)			       (0x00014920 + 0x4*(i0))
1085 #define VIVS_PE_HALTI5_UNK14920__ESIZE				0x00000004
1086 #define VIVS_PE_HALTI5_UNK14920__LEN				0x00000007
1087 
1088 #define VIVS_PE_HALTI5_UNK14940(i0)			       (0x00014940 + 0x4*(i0))
1089 #define VIVS_PE_HALTI5_UNK14940__ESIZE				0x00000004
1090 #define VIVS_PE_HALTI5_UNK14940__LEN				0x00000007
1091 
1092 #define VIVS_PE_HALTI5_UNK14960(i0)			       (0x00014960 + 0x4*(i0))
1093 #define VIVS_PE_HALTI5_UNK14960__ESIZE				0x00000004
1094 #define VIVS_PE_HALTI5_UNK14960__LEN				0x00000007
1095 
1096 #define VIVS_PE_HALTI5_UNK14980(i0)			       (0x00014980 + 0x4*(i0))
1097 #define VIVS_PE_HALTI5_UNK14980__ESIZE				0x00000004
1098 #define VIVS_PE_HALTI5_UNK14980__LEN				0x00000007
1099 
1100 #define VIVS_PE_HALTI5_UNK149A0(i0)			       (0x000149a0 + 0x4*(i0))
1101 #define VIVS_PE_HALTI5_UNK149A0__ESIZE				0x00000004
1102 #define VIVS_PE_HALTI5_UNK149A0__LEN				0x00000007
1103 
1104 #define VIVS_PE_ROBUSTNESS_UNK149C0(i0)			       (0x000149c0 + 0x4*(i0))
1105 #define VIVS_PE_ROBUSTNESS_UNK149C0__ESIZE			0x00000004
1106 #define VIVS_PE_ROBUSTNESS_UNK149C0__LEN			0x00000008
1107 
1108 #define VIVS_CO							0x00000000
1109 
1110 #define VIVS_CO_UNK03008					0x00003008
1111 
1112 #define VIVS_CO_KICKER						0x0000300c
1113 
1114 #define VIVS_CO_UNK03010					0x00003010
1115 
1116 #define VIVS_CO_UNK03014					0x00003014
1117 
1118 #define VIVS_CO_UNK03018					0x00003018
1119 
1120 #define VIVS_CO_UNK0301C					0x0000301c
1121 
1122 #define VIVS_CO_UNK03020					0x00003020
1123 
1124 #define VIVS_CO_UNK03024					0x00003024
1125 
1126 #define VIVS_CO_UNK03040					0x00003040
1127 
1128 #define VIVS_CO_UNK03044					0x00003044
1129 
1130 #define VIVS_CO_UNK03048					0x00003048
1131 
1132 #define VIVS_CO_ICACHE_UNK0304C					0x0000304c
1133 
1134 #define VIVS_CO_SAMPLER(i0)				       (0x00000000 + 0x4*(i0))
1135 #define VIVS_CO_SAMPLER__ESIZE					0x00000004
1136 #define VIVS_CO_SAMPLER__LEN					0x00000008
1137 
1138 #define VIVS_CO_SAMPLER_UNK03060(i0)			       (0x00003060 + 0x4*(i0))
1139 
1140 #define VIVS_CO_SAMPLER_UNK03080(i0)			       (0x00003080 + 0x4*(i0))
1141 
1142 #define VIVS_CO_SAMPLER_UNK030A0(i0)			       (0x000030a0 + 0x4*(i0))
1143 
1144 #define VIVS_CO_SAMPLER_UNK030C0(i0)			       (0x000030c0 + 0x4*(i0))
1145 
1146 #define VIVS_CO_SAMPLER_UNK030E0(i0)			       (0x000030e0 + 0x4*(i0))
1147 
1148 #define VIVS_CO_SAMPLER_UNK03100(i0)			       (0x00003100 + 0x4*(i0))
1149 
1150 #define VIVS_CO_SAMPLER_UNK03120(i0)			       (0x00003120 + 0x4*(i0))
1151 
1152 #define VIVS_CO_SAMPLER_UNK03140(i0)			       (0x00003140 + 0x4*(i0))
1153 
1154 #define VIVS_CO_SAMPLER_UNK03160(i0)			       (0x00003160 + 0x4*(i0))
1155 
1156 #define VIVS_CO_SAMPLER_UNK03180(i0)			       (0x00003180 + 0x4*(i0))
1157 
1158 #define VIVS_CO_SAMPLER_UNK031A0(i0)			       (0x000031a0 + 0x4*(i0))
1159 
1160 #define VIVS_CO_SAMPLER_UNK031C0(i0)			       (0x000031c0 + 0x4*(i0))
1161 
1162 #define VIVS_CO_SAMPLER_UNK031E0(i0)			       (0x000031e0 + 0x4*(i0))
1163 
1164 #define VIVS_CO_ADDR_UNK03200(i0)			       (0x00003200 + 0x20*(i0))
1165 #define VIVS_CO_ADDR_UNK03200__ESIZE				0x00000020
1166 #define VIVS_CO_ADDR_UNK03200__LEN				0x00000008
1167 
1168 #define VIVS_CO_ADDR_UNK03200_PPIPE(i0, i1)		       (0x00003200 + 0x20*(i0) + 0x4*(i1))
1169 #define VIVS_CO_ADDR_UNK03200_PPIPE__ESIZE			0x00000004
1170 #define VIVS_CO_ADDR_UNK03200_PPIPE__LEN			0x00000008
1171 
1172 #define VIVS_RS							0x00000000
1173 
1174 #define VIVS_RS_KICKER						0x00001600
1175 
1176 #define VIVS_RS_CONFIG						0x00001604
1177 #define VIVS_RS_CONFIG_SOURCE_FORMAT__MASK			0x0000001f
1178 #define VIVS_RS_CONFIG_SOURCE_FORMAT__SHIFT			0
1179 #define VIVS_RS_CONFIG_SOURCE_FORMAT(x)				(((x) << VIVS_RS_CONFIG_SOURCE_FORMAT__SHIFT) & VIVS_RS_CONFIG_SOURCE_FORMAT__MASK)
1180 #define VIVS_RS_CONFIG_DOWNSAMPLE_X				0x00000020
1181 #define VIVS_RS_CONFIG_DOWNSAMPLE_Y				0x00000040
1182 #define VIVS_RS_CONFIG_SOURCE_TILED				0x00000080
1183 #define VIVS_RS_CONFIG_DEST_FORMAT__MASK			0x00001f00
1184 #define VIVS_RS_CONFIG_DEST_FORMAT__SHIFT			8
1185 #define VIVS_RS_CONFIG_DEST_FORMAT(x)				(((x) << VIVS_RS_CONFIG_DEST_FORMAT__SHIFT) & VIVS_RS_CONFIG_DEST_FORMAT__MASK)
1186 #define VIVS_RS_CONFIG_DEST_TILED				0x00004000
1187 #define VIVS_RS_CONFIG_SWAP_RB					0x20000000
1188 #define VIVS_RS_CONFIG_FLIP					0x40000000
1189 
1190 #define VIVS_RS_SOURCE_ADDR					0x00001608
1191 
1192 #define VIVS_RS_SOURCE_STRIDE					0x0000160c
1193 #define VIVS_RS_SOURCE_STRIDE_STRIDE__MASK			0x0003ffff
1194 #define VIVS_RS_SOURCE_STRIDE_STRIDE__SHIFT			0
1195 #define VIVS_RS_SOURCE_STRIDE_STRIDE(x)				(((x) << VIVS_RS_SOURCE_STRIDE_STRIDE__SHIFT) & VIVS_RS_SOURCE_STRIDE_STRIDE__MASK)
1196 #define VIVS_RS_SOURCE_STRIDE_MULTI				0x40000000
1197 #define VIVS_RS_SOURCE_STRIDE_TILING				0x80000000
1198 
1199 #define VIVS_RS_DEST_ADDR					0x00001610
1200 
1201 #define VIVS_RS_DEST_STRIDE					0x00001614
1202 #define VIVS_RS_DEST_STRIDE_STRIDE__MASK			0x0003ffff
1203 #define VIVS_RS_DEST_STRIDE_STRIDE__SHIFT			0
1204 #define VIVS_RS_DEST_STRIDE_STRIDE(x)				(((x) << VIVS_RS_DEST_STRIDE_STRIDE__SHIFT) & VIVS_RS_DEST_STRIDE_STRIDE__MASK)
1205 #define VIVS_RS_DEST_STRIDE_MULTI				0x40000000
1206 #define VIVS_RS_DEST_STRIDE_TILING				0x80000000
1207 
1208 #define VIVS_RS_WINDOW_SIZE					0x00001620
1209 #define VIVS_RS_WINDOW_SIZE_HEIGHT__MASK			0xffff0000
1210 #define VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT			16
1211 #define VIVS_RS_WINDOW_SIZE_HEIGHT(x)				(((x) << VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT) & VIVS_RS_WINDOW_SIZE_HEIGHT__MASK)
1212 #define VIVS_RS_WINDOW_SIZE_WIDTH__MASK				0x0000ffff
1213 #define VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT			0
1214 #define VIVS_RS_WINDOW_SIZE_WIDTH(x)				(((x) << VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT) & VIVS_RS_WINDOW_SIZE_WIDTH__MASK)
1215 
1216 #define VIVS_RS_DITHER(i0)				       (0x00001630 + 0x4*(i0))
1217 #define VIVS_RS_DITHER__ESIZE					0x00000004
1218 #define VIVS_RS_DITHER__LEN					0x00000002
1219 
1220 #define VIVS_RS_CLEAR_CONTROL					0x0000163c
1221 #define VIVS_RS_CLEAR_CONTROL_BITS__MASK			0x0000ffff
1222 #define VIVS_RS_CLEAR_CONTROL_BITS__SHIFT			0
1223 #define VIVS_RS_CLEAR_CONTROL_BITS(x)				(((x) << VIVS_RS_CLEAR_CONTROL_BITS__SHIFT) & VIVS_RS_CLEAR_CONTROL_BITS__MASK)
1224 #define VIVS_RS_CLEAR_CONTROL_MODE__MASK			0x00030000
1225 #define VIVS_RS_CLEAR_CONTROL_MODE__SHIFT			16
1226 #define VIVS_RS_CLEAR_CONTROL_MODE_DISABLED			0x00000000
1227 #define VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1			0x00010000
1228 #define VIVS_RS_CLEAR_CONTROL_MODE_ENABLED4			0x00020000
1229 #define VIVS_RS_CLEAR_CONTROL_MODE_ENABLED4_2			0x00030000
1230 
1231 #define VIVS_RS_FILL_VALUE(i0)				       (0x00001640 + 0x4*(i0))
1232 #define VIVS_RS_FILL_VALUE__ESIZE				0x00000004
1233 #define VIVS_RS_FILL_VALUE__LEN					0x00000004
1234 
1235 #define VIVS_RS_EXTRA_CONFIG					0x000016a0
1236 #define VIVS_RS_EXTRA_CONFIG_AA__MASK				0x00000003
1237 #define VIVS_RS_EXTRA_CONFIG_AA__SHIFT				0
1238 #define VIVS_RS_EXTRA_CONFIG_AA(x)				(((x) << VIVS_RS_EXTRA_CONFIG_AA__SHIFT) & VIVS_RS_EXTRA_CONFIG_AA__MASK)
1239 #define VIVS_RS_EXTRA_CONFIG_ENDIAN__MASK			0x00000300
1240 #define VIVS_RS_EXTRA_CONFIG_ENDIAN__SHIFT			8
1241 #define VIVS_RS_EXTRA_CONFIG_ENDIAN(x)				(((x) << VIVS_RS_EXTRA_CONFIG_ENDIAN__SHIFT) & VIVS_RS_EXTRA_CONFIG_ENDIAN__MASK)
1242 #define VIVS_RS_EXTRA_CONFIG_UNK20				0x00100000
1243 #define VIVS_RS_EXTRA_CONFIG_UNK28				0x10000000
1244 
1245 #define VIVS_RS_KICKER_INPLACE					0x000016b0
1246 
1247 #define VIVS_RS_UNK016B4					0x000016b4
1248 
1249 #define VIVS_RS_SINGLE_BUFFER					0x000016b8
1250 #define VIVS_RS_SINGLE_BUFFER_ENABLE				0x00000001
1251 
1252 #define VIVS_RS_PIPE(i0)				       (0x00000000 + 0x4*(i0))
1253 #define VIVS_RS_PIPE__ESIZE					0x00000004
1254 #define VIVS_RS_PIPE__LEN					0x00000008
1255 
1256 #define VIVS_RS_PIPE_SOURCE_ADDR(i0)			       (0x000016c0 + 0x4*(i0))
1257 
1258 #define VIVS_RS_PIPE_DEST_ADDR(i0)			       (0x000016e0 + 0x4*(i0))
1259 
1260 #define VIVS_RS_PIPE_OFFSET(i0)				       (0x00001700 + 0x4*(i0))
1261 #define VIVS_RS_PIPE_OFFSET_X__MASK				0x0000ffff
1262 #define VIVS_RS_PIPE_OFFSET_X__SHIFT				0
1263 #define VIVS_RS_PIPE_OFFSET_X(x)				(((x) << VIVS_RS_PIPE_OFFSET_X__SHIFT) & VIVS_RS_PIPE_OFFSET_X__MASK)
1264 #define VIVS_RS_PIPE_OFFSET_Y__MASK				0xffff0000
1265 #define VIVS_RS_PIPE_OFFSET_Y__SHIFT				16
1266 #define VIVS_RS_PIPE_OFFSET_Y(x)				(((x) << VIVS_RS_PIPE_OFFSET_Y__SHIFT) & VIVS_RS_PIPE_OFFSET_Y__MASK)
1267 
1268 #define VIVS_TS							0x00000000
1269 
1270 #define VIVS_TS_FLUSH_CACHE					0x00001650
1271 #define VIVS_TS_FLUSH_CACHE_FLUSH				0x00000001
1272 
1273 #define VIVS_TS_MEM_CONFIG					0x00001654
1274 #define VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR			0x00000001
1275 #define VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR			0x00000002
1276 #define VIVS_TS_MEM_CONFIG_DEPTH_16BPP				0x00000008
1277 #define VIVS_TS_MEM_CONFIG_DEPTH_AUTO_DISABLE			0x00000010
1278 #define VIVS_TS_MEM_CONFIG_COLOR_AUTO_DISABLE			0x00000020
1279 #define VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION			0x00000040
1280 #define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION			0x00000080
1281 #define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__MASK	0x00000f00
1282 #define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__SHIFT	8
1283 #define VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(x)		(((x) << VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__SHIFT) & VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT__MASK)
1284 #define VIVS_TS_MEM_CONFIG_UNK12				0x00001000
1285 #define VIVS_TS_MEM_CONFIG_HDEPTH_AUTO_DISABLE			0x00002000
1286 #define VIVS_TS_MEM_CONFIG_UNK14				0x00004000
1287 #define VIVS_TS_MEM_CONFIG_UNK21				0x00200000
1288 
1289 #define VIVS_TS_COLOR_STATUS_BASE				0x00001658
1290 
1291 #define VIVS_TS_COLOR_SURFACE_BASE				0x0000165c
1292 
1293 #define VIVS_TS_COLOR_CLEAR_VALUE				0x00001660
1294 
1295 #define VIVS_TS_DEPTH_STATUS_BASE				0x00001664
1296 
1297 #define VIVS_TS_DEPTH_SURFACE_BASE				0x00001668
1298 
1299 #define VIVS_TS_DEPTH_CLEAR_VALUE				0x0000166c
1300 
1301 #define VIVS_TS_DEPTH_AUTO_DISABLE_COUNT			0x00001670
1302 
1303 #define VIVS_TS_COLOR_AUTO_DISABLE_COUNT			0x00001674
1304 
1305 #define VIVS_TS_HDEPTH_STATUS_BASE				0x000016a4
1306 
1307 #define VIVS_TS_HDEPTH_CLEAR_VALUE				0x000016a8
1308 
1309 #define VIVS_TS_HDEPTH_SIZE					0x000016ac
1310 
1311 #define VIVS_TS_COLOR_CLEAR_VALUE_EXT				0x000016bc
1312 
1313 #define VIVS_TS_SAMPLER(i0)				       (0x00000000 + 0x4*(i0))
1314 #define VIVS_TS_SAMPLER__ESIZE					0x00000004
1315 #define VIVS_TS_SAMPLER__LEN					0x00000008
1316 
1317 #define VIVS_TS_SAMPLER_CONFIG(i0)			       (0x00001720 + 0x4*(i0))
1318 #define VIVS_TS_SAMPLER_CONFIG_ENABLE__MASK			0x00000003
1319 #define VIVS_TS_SAMPLER_CONFIG_ENABLE__SHIFT			0
1320 #define VIVS_TS_SAMPLER_CONFIG_ENABLE(x)			(((x) << VIVS_TS_SAMPLER_CONFIG_ENABLE__SHIFT) & VIVS_TS_SAMPLER_CONFIG_ENABLE__MASK)
1321 #define VIVS_TS_SAMPLER_CONFIG_FORMAT__MASK			0x000000f0
1322 #define VIVS_TS_SAMPLER_CONFIG_FORMAT__SHIFT			4
1323 #define VIVS_TS_SAMPLER_CONFIG_FORMAT(x)			(((x) << VIVS_TS_SAMPLER_CONFIG_FORMAT__SHIFT) & VIVS_TS_SAMPLER_CONFIG_FORMAT__MASK)
1324 #define VIVS_TS_SAMPLER_CONFIG_UNK11__MASK			0x00003800
1325 #define VIVS_TS_SAMPLER_CONFIG_UNK11__SHIFT			11
1326 #define VIVS_TS_SAMPLER_CONFIG_UNK11(x)				(((x) << VIVS_TS_SAMPLER_CONFIG_UNK11__SHIFT) & VIVS_TS_SAMPLER_CONFIG_UNK11__MASK)
1327 
1328 #define VIVS_TS_SAMPLER_STATUS_BASE(i0)			       (0x00001740 + 0x4*(i0))
1329 
1330 #define VIVS_TS_SAMPLER_CLEAR_VALUE(i0)			       (0x00001760 + 0x4*(i0))
1331 
1332 #define VIVS_TS_SAMPLER_CLEAR_VALUE2(i0)		       (0x00001780 + 0x4*(i0))
1333 
1334 #define VIVS_TS_SAMPLER_SURFACE_BASE(i0)		       (0x00001a80 + 0x4*(i0))
1335 
1336 #define VIVS_TS_RT(i0)					       (0x00000000 + 0x4*(i0))
1337 #define VIVS_TS_RT__ESIZE					0x00000004
1338 #define VIVS_TS_RT__LEN						0x00000008
1339 
1340 #define VIVS_TS_RT_UNK017A0(i0)				       (0x000017a0 + 0x4*(i0))
1341 
1342 #define VIVS_TS_RT_STATUS_BASE(i0)			       (0x000017c0 + 0x4*(i0))
1343 
1344 #define VIVS_TS_RT_SURFACE_BASE(i0)			       (0x000017e0 + 0x4*(i0))
1345 
1346 #define VIVS_TS_RT_CLEAR_VALUE(i0)			       (0x00001a00 + 0x4*(i0))
1347 
1348 #define VIVS_TS_RT_CLEAR_VALUE2(i0)			       (0x00001a20 + 0x4*(i0))
1349 
1350 #define VIVS_TS_RT_UNK01A40(i0)				       (0x00001a40 + 0x4*(i0))
1351 
1352 #define VIVS_YUV						0x00000000
1353 
1354 #define VIVS_YUV_UNK01678					0x00001678
1355 
1356 #define VIVS_YUV_UNK0167C					0x0000167c
1357 
1358 #define VIVS_YUV_UNK01680					0x00001680
1359 
1360 #define VIVS_YUV_UNK01684					0x00001684
1361 
1362 #define VIVS_YUV_UNK01688					0x00001688
1363 
1364 #define VIVS_YUV_UNK0168C					0x0000168c
1365 
1366 #define VIVS_YUV_UNK01690					0x00001690
1367 
1368 #define VIVS_YUV_UNK01694					0x00001694
1369 
1370 #define VIVS_YUV_UNK01698					0x00001698
1371 
1372 #define VIVS_YUV_UNK0169C					0x0000169c
1373 
1374 #define VIVS_TE							0x00000000
1375 
1376 #define VIVS_TE_SAMPLER(i0)				       (0x00000000 + 0x4*(i0))
1377 #define VIVS_TE_SAMPLER__ESIZE					0x00000004
1378 #define VIVS_TE_SAMPLER__LEN					0x0000000c
1379 
1380 #define VIVS_TE_SAMPLER_CONFIG0(i0)			       (0x00002000 + 0x4*(i0))
1381 #define VIVS_TE_SAMPLER_CONFIG0_TYPE__MASK			0x00000007
1382 #define VIVS_TE_SAMPLER_CONFIG0_TYPE__SHIFT			0
1383 #define VIVS_TE_SAMPLER_CONFIG0_TYPE(x)				(((x) << VIVS_TE_SAMPLER_CONFIG0_TYPE__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_TYPE__MASK)
1384 #define VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK			0x00000018
1385 #define VIVS_TE_SAMPLER_CONFIG0_UWRAP__SHIFT			3
1386 #define VIVS_TE_SAMPLER_CONFIG0_UWRAP(x)			(((x) << VIVS_TE_SAMPLER_CONFIG0_UWRAP__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK)
1387 #define VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK			0x00000060
1388 #define VIVS_TE_SAMPLER_CONFIG0_VWRAP__SHIFT			5
1389 #define VIVS_TE_SAMPLER_CONFIG0_VWRAP(x)			(((x) << VIVS_TE_SAMPLER_CONFIG0_VWRAP__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK)
1390 #define VIVS_TE_SAMPLER_CONFIG0_MIN__MASK			0x00000180
1391 #define VIVS_TE_SAMPLER_CONFIG0_MIN__SHIFT			7
1392 #define VIVS_TE_SAMPLER_CONFIG0_MIN(x)				(((x) << VIVS_TE_SAMPLER_CONFIG0_MIN__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_MIN__MASK)
1393 #define VIVS_TE_SAMPLER_CONFIG0_MIP__MASK			0x00000600
1394 #define VIVS_TE_SAMPLER_CONFIG0_MIP__SHIFT			9
1395 #define VIVS_TE_SAMPLER_CONFIG0_MIP(x)				(((x) << VIVS_TE_SAMPLER_CONFIG0_MIP__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_MIP__MASK)
1396 #define VIVS_TE_SAMPLER_CONFIG0_MAG__MASK			0x00001800
1397 #define VIVS_TE_SAMPLER_CONFIG0_MAG__SHIFT			11
1398 #define VIVS_TE_SAMPLER_CONFIG0_MAG(x)				(((x) << VIVS_TE_SAMPLER_CONFIG0_MAG__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_MAG__MASK)
1399 #define VIVS_TE_SAMPLER_CONFIG0_FORMAT__MASK			0x0003e000
1400 #define VIVS_TE_SAMPLER_CONFIG0_FORMAT__SHIFT			13
1401 #define VIVS_TE_SAMPLER_CONFIG0_FORMAT(x)			(((x) << VIVS_TE_SAMPLER_CONFIG0_FORMAT__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_FORMAT__MASK)
1402 #define VIVS_TE_SAMPLER_CONFIG0_ROUND_UV			0x00080000
1403 #define VIVS_TE_SAMPLER_CONFIG0_ENDIAN__MASK			0x00c00000
1404 #define VIVS_TE_SAMPLER_CONFIG0_ENDIAN__SHIFT			22
1405 #define VIVS_TE_SAMPLER_CONFIG0_ENDIAN(x)			(((x) << VIVS_TE_SAMPLER_CONFIG0_ENDIAN__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_ENDIAN__MASK)
1406 #define VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__MASK		0xff000000
1407 #define VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT		24
1408 #define VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY(x)			(((x) << VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__MASK)
1409 
1410 #define VIVS_TE_SAMPLER_SIZE(i0)			       (0x00002040 + 0x4*(i0))
1411 #define VIVS_TE_SAMPLER_SIZE_WIDTH__MASK			0x0000ffff
1412 #define VIVS_TE_SAMPLER_SIZE_WIDTH__SHIFT			0
1413 #define VIVS_TE_SAMPLER_SIZE_WIDTH(x)				(((x) << VIVS_TE_SAMPLER_SIZE_WIDTH__SHIFT) & VIVS_TE_SAMPLER_SIZE_WIDTH__MASK)
1414 #define VIVS_TE_SAMPLER_SIZE_HEIGHT__MASK			0xffff0000
1415 #define VIVS_TE_SAMPLER_SIZE_HEIGHT__SHIFT			16
1416 #define VIVS_TE_SAMPLER_SIZE_HEIGHT(x)				(((x) << VIVS_TE_SAMPLER_SIZE_HEIGHT__SHIFT) & VIVS_TE_SAMPLER_SIZE_HEIGHT__MASK)
1417 
1418 #define VIVS_TE_SAMPLER_LOG_SIZE(i0)			       (0x00002080 + 0x4*(i0))
1419 #define VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__MASK			0x000003ff
1420 #define VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__SHIFT			0
1421 #define VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(x)			(((x) << VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__SHIFT) & VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__MASK)
1422 #define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__MASK			0x000ffc00
1423 #define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT			10
1424 #define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(x)			(((x) << VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT) & VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__MASK)
1425 #define VIVS_TE_SAMPLER_LOG_SIZE_ASTC				0x10000000
1426 #define VIVS_TE_SAMPLER_LOG_SIZE_RGB				0x20000000
1427 #define VIVS_TE_SAMPLER_LOG_SIZE_SRGB				0x80000000
1428 
1429 #define VIVS_TE_SAMPLER_LOD_CONFIG(i0)			       (0x000020c0 + 0x4*(i0))
1430 #define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS_ENABLE			0x00000001
1431 #define VIVS_TE_SAMPLER_LOD_CONFIG_MAX__MASK			0x000007fe
1432 #define VIVS_TE_SAMPLER_LOD_CONFIG_MAX__SHIFT			1
1433 #define VIVS_TE_SAMPLER_LOD_CONFIG_MAX(x)			(((x) << VIVS_TE_SAMPLER_LOD_CONFIG_MAX__SHIFT) & VIVS_TE_SAMPLER_LOD_CONFIG_MAX__MASK)
1434 #define VIVS_TE_SAMPLER_LOD_CONFIG_MIN__MASK			0x001ff800
1435 #define VIVS_TE_SAMPLER_LOD_CONFIG_MIN__SHIFT			11
1436 #define VIVS_TE_SAMPLER_LOD_CONFIG_MIN(x)			(((x) << VIVS_TE_SAMPLER_LOD_CONFIG_MIN__SHIFT) & VIVS_TE_SAMPLER_LOD_CONFIG_MIN__MASK)
1437 #define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__MASK			0x7fe00000
1438 #define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__SHIFT			21
1439 #define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS(x)			(((x) << VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__SHIFT) & VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__MASK)
1440 
1441 #define VIVS_TE_SAMPLER_UNK02100(i0)			       (0x00002100 + 0x4*(i0))
1442 
1443 #define VIVS_TE_SAMPLER_UNK02140(i0)			       (0x00002140 + 0x4*(i0))
1444 
1445 #define VIVS_TE_SAMPLER_3D_CONFIG(i0)			       (0x00002180 + 0x4*(i0))
1446 #define VIVS_TE_SAMPLER_3D_CONFIG_DEPTH__MASK			0x00003fff
1447 #define VIVS_TE_SAMPLER_3D_CONFIG_DEPTH__SHIFT			0
1448 #define VIVS_TE_SAMPLER_3D_CONFIG_DEPTH(x)			(((x) << VIVS_TE_SAMPLER_3D_CONFIG_DEPTH__SHIFT) & VIVS_TE_SAMPLER_3D_CONFIG_DEPTH__MASK)
1449 #define VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH__MASK		0x03ff0000
1450 #define VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH__SHIFT		16
1451 #define VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH(x)			(((x) << VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH__SHIFT) & VIVS_TE_SAMPLER_3D_CONFIG_LOG_DEPTH__MASK)
1452 #define VIVS_TE_SAMPLER_3D_CONFIG_WRAP__MASK			0x30000000
1453 #define VIVS_TE_SAMPLER_3D_CONFIG_WRAP__SHIFT			28
1454 #define VIVS_TE_SAMPLER_3D_CONFIG_WRAP(x)			(((x) << VIVS_TE_SAMPLER_3D_CONFIG_WRAP__SHIFT) & VIVS_TE_SAMPLER_3D_CONFIG_WRAP__MASK)
1455 
1456 #define VIVS_TE_SAMPLER_CONFIG1(i0)			       (0x000021c0 + 0x4*(i0))
1457 #define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__MASK		0x0000003f
1458 #define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT		0
1459 #define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__MASK)
1460 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__MASK			0x00000700
1461 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT		8
1462 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__MASK)
1463 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__MASK			0x00007000
1464 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT		12
1465 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__MASK)
1466 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__MASK			0x00070000
1467 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT		16
1468 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__MASK)
1469 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__MASK			0x00700000
1470 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT		20
1471 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__MASK)
1472 #define VIVS_TE_SAMPLER_CONFIG1_CACHE_MODE__MASK		0x00800000
1473 #define VIVS_TE_SAMPLER_CONFIG1_CACHE_MODE__SHIFT		23
1474 #define VIVS_TE_SAMPLER_CONFIG1_CACHE_MODE(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_CACHE_MODE__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_CACHE_MODE__MASK)
1475 #define VIVS_TE_SAMPLER_CONFIG1_TEXTURE_ARRAY			0x01000000
1476 #define VIVS_TE_SAMPLER_CONFIG1_UNK25				0x02000000
1477 #define VIVS_TE_SAMPLER_CONFIG1_HALIGN__MASK			0x1c000000
1478 #define VIVS_TE_SAMPLER_CONFIG1_HALIGN__SHIFT			26
1479 #define VIVS_TE_SAMPLER_CONFIG1_HALIGN(x)			(((x) << VIVS_TE_SAMPLER_CONFIG1_HALIGN__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_HALIGN__MASK)
1480 #define VIVS_TE_SAMPLER_CONFIG1_USE_TS				0x40000000
1481 
1482 #define VIVS_TE_SAMPLER_UNK02200(i0)			       (0x00002200 + 0x4*(i0))
1483 
1484 #define VIVS_TE_SAMPLER_UNK02240(i0)			       (0x00002240 + 0x4*(i0))
1485 
1486 #define VIVS_TE_SAMPLER_LOD_ADDR(i0, i1)		       (0x00002400 + 0x4*(i0) + 0x40*(i1))
1487 #define VIVS_TE_SAMPLER_LOD_ADDR__ESIZE				0x00000040
1488 #define VIVS_TE_SAMPLER_LOD_ADDR__LEN				0x0000000e
1489 
1490 #define VIVS_TE_SAMPLER_LINEAR_STRIDE(i0, i1)		       (0x00002c00 + 0x4*(i0) + 0x40*(i1))
1491 #define VIVS_TE_SAMPLER_LINEAR_STRIDE__ESIZE			0x00000040
1492 #define VIVS_TE_SAMPLER_LINEAR_STRIDE__LEN			0x0000000e
1493 
1494 #define VIVS_NTE						0x00000000
1495 
1496 #define VIVS_NTE_SAMPLER(i0)				       (0x00000000 + 0x4*(i0))
1497 #define VIVS_NTE_SAMPLER__ESIZE					0x00000004
1498 #define VIVS_NTE_SAMPLER__LEN					0x00000020
1499 
1500 #define VIVS_NTE_SAMPLER_CONFIG0(i0)			       (0x00010000 + 0x4*(i0))
1501 #define VIVS_NTE_SAMPLER_CONFIG0_TYPE__MASK			0x00000007
1502 #define VIVS_NTE_SAMPLER_CONFIG0_TYPE__SHIFT			0
1503 #define VIVS_NTE_SAMPLER_CONFIG0_TYPE(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_TYPE__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_TYPE__MASK)
1504 #define VIVS_NTE_SAMPLER_CONFIG0_UWRAP__MASK			0x00000018
1505 #define VIVS_NTE_SAMPLER_CONFIG0_UWRAP__SHIFT			3
1506 #define VIVS_NTE_SAMPLER_CONFIG0_UWRAP(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_UWRAP__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_UWRAP__MASK)
1507 #define VIVS_NTE_SAMPLER_CONFIG0_VWRAP__MASK			0x00000060
1508 #define VIVS_NTE_SAMPLER_CONFIG0_VWRAP__SHIFT			5
1509 #define VIVS_NTE_SAMPLER_CONFIG0_VWRAP(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_VWRAP__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_VWRAP__MASK)
1510 #define VIVS_NTE_SAMPLER_CONFIG0_MIN__MASK			0x00000180
1511 #define VIVS_NTE_SAMPLER_CONFIG0_MIN__SHIFT			7
1512 #define VIVS_NTE_SAMPLER_CONFIG0_MIN(x)				(((x) << VIVS_NTE_SAMPLER_CONFIG0_MIN__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_MIN__MASK)
1513 #define VIVS_NTE_SAMPLER_CONFIG0_MIP__MASK			0x00000600
1514 #define VIVS_NTE_SAMPLER_CONFIG0_MIP__SHIFT			9
1515 #define VIVS_NTE_SAMPLER_CONFIG0_MIP(x)				(((x) << VIVS_NTE_SAMPLER_CONFIG0_MIP__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_MIP__MASK)
1516 #define VIVS_NTE_SAMPLER_CONFIG0_MAG__MASK			0x00001800
1517 #define VIVS_NTE_SAMPLER_CONFIG0_MAG__SHIFT			11
1518 #define VIVS_NTE_SAMPLER_CONFIG0_MAG(x)				(((x) << VIVS_NTE_SAMPLER_CONFIG0_MAG__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_MAG__MASK)
1519 #define VIVS_NTE_SAMPLER_CONFIG0_FORMAT__MASK			0x0003e000
1520 #define VIVS_NTE_SAMPLER_CONFIG0_FORMAT__SHIFT			13
1521 #define VIVS_NTE_SAMPLER_CONFIG0_FORMAT(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_FORMAT__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_FORMAT__MASK)
1522 #define VIVS_NTE_SAMPLER_CONFIG0_ROUND_UV			0x00080000
1523 #define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__MASK			0x00c00000
1524 #define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__SHIFT			22
1525 #define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__MASK)
1526 #define VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__MASK		0xff000000
1527 #define VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT		24
1528 #define VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__MASK)
1529 
1530 #define VIVS_NTE_SAMPLER_SIZE(i0)			       (0x00010080 + 0x4*(i0))
1531 #define VIVS_NTE_SAMPLER_SIZE_WIDTH__MASK			0x0000ffff
1532 #define VIVS_NTE_SAMPLER_SIZE_WIDTH__SHIFT			0
1533 #define VIVS_NTE_SAMPLER_SIZE_WIDTH(x)				(((x) << VIVS_NTE_SAMPLER_SIZE_WIDTH__SHIFT) & VIVS_NTE_SAMPLER_SIZE_WIDTH__MASK)
1534 #define VIVS_NTE_SAMPLER_SIZE_HEIGHT__MASK			0xffff0000
1535 #define VIVS_NTE_SAMPLER_SIZE_HEIGHT__SHIFT			16
1536 #define VIVS_NTE_SAMPLER_SIZE_HEIGHT(x)				(((x) << VIVS_NTE_SAMPLER_SIZE_HEIGHT__SHIFT) & VIVS_NTE_SAMPLER_SIZE_HEIGHT__MASK)
1537 
1538 #define VIVS_NTE_SAMPLER_LOG_SIZE(i0)			       (0x00010100 + 0x4*(i0))
1539 #define VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__MASK			0x000003ff
1540 #define VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__SHIFT			0
1541 #define VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH(x)			(((x) << VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__SHIFT) & VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__MASK)
1542 #define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__MASK			0x000ffc00
1543 #define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT			10
1544 #define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT(x)			(((x) << VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT) & VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__MASK)
1545 #define VIVS_NTE_SAMPLER_LOG_SIZE_ASTC				0x10000000
1546 #define VIVS_NTE_SAMPLER_LOG_SIZE_RGB				0x20000000
1547 #define VIVS_NTE_SAMPLER_LOG_SIZE_SRGB				0x80000000
1548 
1549 #define VIVS_NTE_SAMPLER_LOD_CONFIG(i0)			       (0x00010180 + 0x4*(i0))
1550 #define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS_ENABLE			0x00000001
1551 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__MASK			0x000007fe
1552 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__SHIFT			1
1553 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MAX(x)			(((x) << VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__SHIFT) & VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__MASK)
1554 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__MASK			0x001ff800
1555 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__SHIFT			11
1556 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MIN(x)			(((x) << VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__SHIFT) & VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__MASK)
1557 #define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__MASK			0x7fe00000
1558 #define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__SHIFT			21
1559 #define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS(x)			(((x) << VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__SHIFT) & VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__MASK)
1560 
1561 #define VIVS_NTE_SAMPLER_UNK10200(i0)			       (0x00010200 + 0x4*(i0))
1562 
1563 #define VIVS_NTE_SAMPLER_UNK10280(i0)			       (0x00010280 + 0x4*(i0))
1564 
1565 #define VIVS_NTE_SAMPLER_3D_CONFIG(i0)			       (0x00010300 + 0x4*(i0))
1566 #define VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__MASK			0x00003fff
1567 #define VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__SHIFT			0
1568 #define VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH(x)			(((x) << VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__SHIFT) & VIVS_NTE_SAMPLER_3D_CONFIG_DEPTH__MASK)
1569 #define VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__MASK		0x03ff0000
1570 #define VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__SHIFT		16
1571 #define VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH(x)			(((x) << VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__SHIFT) & VIVS_NTE_SAMPLER_3D_CONFIG_LOG_DEPTH__MASK)
1572 #define VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__MASK			0x30000000
1573 #define VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__SHIFT			28
1574 #define VIVS_NTE_SAMPLER_3D_CONFIG_WRAP(x)			(((x) << VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__SHIFT) & VIVS_NTE_SAMPLER_3D_CONFIG_WRAP__MASK)
1575 
1576 #define VIVS_NTE_SAMPLER_CONFIG1(i0)			       (0x00010380 + 0x4*(i0))
1577 #define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__MASK		0x0000003f
1578 #define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT		0
1579 #define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__MASK)
1580 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__MASK		0x00000700
1581 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT		8
1582 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__MASK)
1583 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__MASK		0x00007000
1584 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT		12
1585 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__MASK)
1586 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__MASK		0x00070000
1587 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT		16
1588 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__MASK)
1589 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__MASK		0x00700000
1590 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT		20
1591 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__MASK)
1592 #define VIVS_NTE_SAMPLER_CONFIG1_CACHE_MODE__MASK		0x00800000
1593 #define VIVS_NTE_SAMPLER_CONFIG1_CACHE_MODE__SHIFT		23
1594 #define VIVS_NTE_SAMPLER_CONFIG1_CACHE_MODE(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_CACHE_MODE__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_CACHE_MODE__MASK)
1595 #define VIVS_NTE_SAMPLER_CONFIG1_TEXTURE_ARRAY			0x01000000
1596 #define VIVS_NTE_SAMPLER_CONFIG1_UNK25				0x02000000
1597 #define VIVS_NTE_SAMPLER_CONFIG1_HALIGN__MASK			0x1c000000
1598 #define VIVS_NTE_SAMPLER_CONFIG1_HALIGN__SHIFT			26
1599 #define VIVS_NTE_SAMPLER_CONFIG1_HALIGN(x)			(((x) << VIVS_NTE_SAMPLER_CONFIG1_HALIGN__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_HALIGN__MASK)
1600 #define VIVS_NTE_SAMPLER_CONFIG1_USE_TS				0x40000000
1601 
1602 #define VIVS_NTE_SAMPLER_UNK10400(i0)			       (0x00010400 + 0x4*(i0))
1603 
1604 #define VIVS_NTE_SAMPLER_UNK10480(i0)			       (0x00010480 + 0x4*(i0))
1605 
1606 #define VIVS_NTE_SAMPLER_ASTC0(i0)			       (0x00010500 + 0x4*(i0))
1607 #define VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__MASK		0x000000ff
1608 #define VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__SHIFT		0
1609 #define VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT(x)			(((x) << VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT__MASK)
1610 #define VIVS_NTE_SAMPLER_ASTC0_UNK8__MASK			0x0000ff00
1611 #define VIVS_NTE_SAMPLER_ASTC0_UNK8__SHIFT			8
1612 #define VIVS_NTE_SAMPLER_ASTC0_UNK8(x)				(((x) << VIVS_NTE_SAMPLER_ASTC0_UNK8__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_UNK8__MASK)
1613 #define VIVS_NTE_SAMPLER_ASTC0_UNK16__MASK			0x00ff0000
1614 #define VIVS_NTE_SAMPLER_ASTC0_UNK16__SHIFT			16
1615 #define VIVS_NTE_SAMPLER_ASTC0_UNK16(x)				(((x) << VIVS_NTE_SAMPLER_ASTC0_UNK16__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_UNK16__MASK)
1616 #define VIVS_NTE_SAMPLER_ASTC0_UNK24__MASK			0xff000000
1617 #define VIVS_NTE_SAMPLER_ASTC0_UNK24__SHIFT			24
1618 #define VIVS_NTE_SAMPLER_ASTC0_UNK24(x)				(((x) << VIVS_NTE_SAMPLER_ASTC0_UNK24__SHIFT) & VIVS_NTE_SAMPLER_ASTC0_UNK24__MASK)
1619 
1620 #define VIVS_NTE_SAMPLER_ASTC1(i0)			       (0x00010580 + 0x4*(i0))
1621 
1622 #define VIVS_NTE_SAMPLER_ASTC2(i0)			       (0x00010600 + 0x4*(i0))
1623 
1624 #define VIVS_NTE_SAMPLER_ASTC3(i0)			       (0x00010600 + 0x4*(i0))
1625 
1626 #define VIVS_NTE_SAMPLER_BASELOD(i0)			       (0x00010700 + 0x4*(i0))
1627 #define VIVS_NTE_SAMPLER_BASELOD_UNK23				0x00800000
1628 #define VIVS_NTE_SAMPLER_BASELOD_BASELOD__MASK			0x0000000f
1629 #define VIVS_NTE_SAMPLER_BASELOD_BASELOD__SHIFT			0
1630 #define VIVS_NTE_SAMPLER_BASELOD_BASELOD(x)			(((x) << VIVS_NTE_SAMPLER_BASELOD_BASELOD__SHIFT) & VIVS_NTE_SAMPLER_BASELOD_BASELOD__MASK)
1631 #define VIVS_NTE_SAMPLER_BASELOD_MAXLOD__MASK			0x00000f00
1632 #define VIVS_NTE_SAMPLER_BASELOD_MAXLOD__SHIFT			8
1633 #define VIVS_NTE_SAMPLER_BASELOD_MAXLOD(x)			(((x) << VIVS_NTE_SAMPLER_BASELOD_MAXLOD__SHIFT) & VIVS_NTE_SAMPLER_BASELOD_MAXLOD__MASK)
1634 
1635 #define VIVS_NTE_SAMPLER_UNK10780(i0)			       (0x00010780 + 0x4*(i0))
1636 
1637 #define VIVS_NTE_SAMPLER_FRAC_UNK11000(i0)		       (0x00011000 + 0x4*(i0))
1638 
1639 #define VIVS_NTE_SAMPLER_FRAC_UNK11080(i0)		       (0x00011080 + 0x4*(i0))
1640 
1641 #define VIVS_NTE_SAMPLER_FRAC_UNK11100(i0)		       (0x00011100 + 0x4*(i0))
1642 
1643 #define VIVS_NTE_SAMPLER_FRAC_UNK11180(i0)		       (0x00011180 + 0x4*(i0))
1644 
1645 #define VIVS_NTE_SAMPLER_HALTI4_UNK11200(i0)		       (0x00011200 + 0x4*(i0))
1646 
1647 #define VIVS_NTE_SAMPLER_HALTI4_UNK11280(i0)		       (0x00011280 + 0x4*(i0))
1648 
1649 #define VIVS_NTE_SAMPLER_FRAC_UNK11300(i0)		       (0x00011300 + 0x4*(i0))
1650 
1651 #define VIVS_NTE_SAMPLER_ADDR(i0)			       (0x00010800 + 0x40*(i0))
1652 #define VIVS_NTE_SAMPLER_ADDR__ESIZE				0x00000040
1653 #define VIVS_NTE_SAMPLER_ADDR__LEN				0x00000020
1654 
1655 #define VIVS_NTE_SAMPLER_ADDR_LOD(i0, i1)		       (0x00010800 + 0x40*(i0) + 0x4*(i1))
1656 #define VIVS_NTE_SAMPLER_ADDR_LOD__ESIZE			0x00000004
1657 #define VIVS_NTE_SAMPLER_ADDR_LOD__LEN				0x0000000e
1658 
1659 #define VIVS_NTE_UNK12000(i0)				       (0x00012000 + 0x4*(i0))
1660 #define VIVS_NTE_UNK12000__ESIZE				0x00000004
1661 #define VIVS_NTE_UNK12000__LEN					0x00000100
1662 
1663 #define VIVS_NTE_UNK12400(i0)				       (0x00012400 + 0x4*(i0))
1664 #define VIVS_NTE_UNK12400__ESIZE				0x00000004
1665 #define VIVS_NTE_UNK12400__LEN					0x00000100
1666 
1667 #define VIVS_NTE_HALTI3_UNK14C00(i0)			       (0x00014c00 + 0x4*(i0))
1668 #define VIVS_NTE_HALTI3_UNK14C00__ESIZE				0x00000004
1669 #define VIVS_NTE_HALTI3_UNK14C00__LEN				0x00000010
1670 
1671 #define VIVS_NTE_DESCRIPTOR_UNK14C40				0x00014c40
1672 #define VIVS_NTE_DESCRIPTOR_UNK14C40_UNK0			0x00000001
1673 
1674 #define VIVS_NTE_DESCRIPTOR_FLUSH				0x00014c44
1675 #define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__MASK			0xf0000000
1676 #define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__SHIFT			28
1677 #define VIVS_NTE_DESCRIPTOR_FLUSH_UNK28(x)			(((x) << VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__SHIFT) & VIVS_NTE_DESCRIPTOR_FLUSH_UNK28__MASK)
1678 
1679 #define VIVS_NTE_DESCRIPTOR_INVALIDATE				0x00014c48
1680 #define VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__MASK		0x000001ff
1681 #define VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__SHIFT		0
1682 #define VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX(x)			(((x) << VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__SHIFT) & VIVS_NTE_DESCRIPTOR_INVALIDATE_IDX__MASK)
1683 #define VIVS_NTE_DESCRIPTOR_INVALIDATE_UNK29			0x20000000
1684 
1685 #define VIVS_NTE_DESCRIPTOR(i0)				       (0x00000000 + 0x4*(i0))
1686 #define VIVS_NTE_DESCRIPTOR__ESIZE				0x00000004
1687 #define VIVS_NTE_DESCRIPTOR__LEN				0x00000080
1688 
1689 #define VIVS_NTE_DESCRIPTOR_ADDR_MIRROR(i0)		       (0x00015800 + 0x4*(i0))
1690 
1691 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_MIRROR(i0)		       (0x00015a00 + 0x4*(i0))
1692 
1693 #define VIVS_NTE_DESCRIPTOR_ADDR(i0)			       (0x00015c00 + 0x4*(i0))
1694 
1695 #define VIVS_NTE_DESCRIPTOR_TX_CTRL(i0)			       (0x00015e00 + 0x4*(i0))
1696 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE__MASK		0x00000003
1697 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE__SHIFT		0
1698 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE(x)		(((x) << VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE__SHIFT) & VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_ENABLE__MASK)
1699 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__MASK		0x0000001c
1700 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__SHIFT		2
1701 #define VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX(x)			(((x) << VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__SHIFT) & VIVS_NTE_DESCRIPTOR_TX_CTRL_TS_INDEX__MASK)
1702 
1703 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIRROR(i0)	       (0x00016000 + 0x4*(i0))
1704 
1705 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_MIRROR(i0)	       (0x00016200 + 0x4*(i0))
1706 
1707 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIRROR(i0)	       (0x00016400 + 0x4*(i0))
1708 
1709 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_MIRROR(i0)	       (0x00016600 + 0x4*(i0))
1710 
1711 #define VIVS_NTE_DESCRIPTOR_UNK17400_MIRROR(i0)		       (0x00016800 + 0x4*(i0))
1712 
1713 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0(i0)		       (0x00016c00 + 0x4*(i0))
1714 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__MASK		0x00000007
1715 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__SHIFT		0
1716 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP(x)			(((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UWRAP__MASK)
1717 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__MASK		0x00000038
1718 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__SHIFT		3
1719 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP(x)			(((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_VWRAP__MASK)
1720 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__MASK		0x000001c0
1721 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__SHIFT		6
1722 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP(x)			(((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_WWRAP__MASK)
1723 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__MASK		0x00000600
1724 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__SHIFT		9
1725 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN(x)			(((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIN__MASK)
1726 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__MASK		0x00001800
1727 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__SHIFT		11
1728 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP(x)			(((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MIP__MASK)
1729 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__MASK		0x00006000
1730 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__SHIFT		13
1731 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG(x)			(((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_MAG__MASK)
1732 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UNK21			0x00200000
1733 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_UNK22			0x00400000
1734 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL0_RGB			0x00800000
1735 
1736 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1(i0)		       (0x00016e00 + 0x4*(i0))
1737 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK1			0x00000002
1738 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_SRGB			0x00000004
1739 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK3			0x00000008
1740 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__MASK		0x00000030
1741 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__SHIFT		4
1742 #define VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4(x)			(((x) << VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_CTRL1_UNK4__MASK)
1743 
1744 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX(i0)		       (0x00017000 + 0x4*(i0))
1745 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__MASK		0x0000ffff
1746 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__SHIFT		0
1747 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX(x)		(((x) << VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MAX__MASK)
1748 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__MASK		0xffff0000
1749 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__SHIFT		16
1750 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN(x)		(((x) << VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_LOD_MINMAX_MIN__MASK)
1751 
1752 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS(i0)		       (0x00017200 + 0x4*(i0))
1753 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__MASK		0x0000ffff
1754 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__SHIFT		0
1755 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS(x)		(((x) << VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__SHIFT) & VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_BIAS__MASK)
1756 #define VIVS_NTE_DESCRIPTOR_SAMP_LOD_BIAS_ENABLE		0x00010000
1757 
1758 #define VIVS_NTE_DESCRIPTOR_UNK17400(i0)		       (0x00017400 + 0x4*(i0))
1759 
1760 #define VIVS_SH							0x00000000
1761 
1762 #define VIVS_SH_CONFIG						0x00015600
1763 #define VIVS_SH_CONFIG_RTNE_ROUNDING				0x00000002
1764 #define VIVS_SH_CONFIG_DUAL16					0x00000004
1765 
1766 #define VIVS_SH_UNK20000(i0)				       (0x00020000 + 0x4*(i0))
1767 #define VIVS_SH_UNK20000__ESIZE					0x00000004
1768 #define VIVS_SH_UNK20000__LEN					0x00002000
1769 
1770 #define VIVS_SH_INST_MEM(i0)				       (0x0000c000 + 0x4*(i0))
1771 #define VIVS_SH_INST_MEM__ESIZE					0x00000004
1772 #define VIVS_SH_INST_MEM__LEN					0x00001000
1773 
1774 #define VIVS_SH_INST_MEM_MIRROR(i0)			       (0x00008000 + 0x4*(i0))
1775 #define VIVS_SH_INST_MEM_MIRROR__ESIZE				0x00000004
1776 #define VIVS_SH_INST_MEM_MIRROR__LEN				0x00001000
1777 
1778 #define VIVS_SH_UNIFORMS(i0)				       (0x00030000 + 0x4*(i0))
1779 #define VIVS_SH_UNIFORMS__ESIZE					0x00000004
1780 #define VIVS_SH_UNIFORMS__LEN					0x00000800
1781 
1782 #define VIVS_SH_HALTI5_UNIFORMS_MIRROR(i0)		       (0x00034000 + 0x4*(i0))
1783 #define VIVS_SH_HALTI5_UNIFORMS_MIRROR__ESIZE			0x00000004
1784 #define VIVS_SH_HALTI5_UNIFORMS_MIRROR__LEN			0x00000800
1785 
1786 #define VIVS_SH_HALTI5_UNIFORMS(i0)			       (0x00036000 + 0x4*(i0))
1787 #define VIVS_SH_HALTI5_UNIFORMS__ESIZE				0x00000004
1788 #define VIVS_SH_HALTI5_UNIFORMS__LEN				0x00000800
1789 
1790 
1791 #endif /* STATE_3D_XML */
1792