Searched refs:VIV_ISA_WORD_1_SRC0_REG (Results 1 – 2 of 2) sorted by relevance
84 VIV_ISA_WORD_1_SRC0_REG(inst->src[0].reg) | in etna_assemble()
260 #define VIV_ISA_WORD_1_SRC0_REG(x) (((x) << VIV_ISA_WORD_1_SRC0_REG__SHIFT) & VIV_ISA_WORD_1_SRC… macro