| /external/llvm/lib/CodeGen/ |
| D | MachineSSAUpdater.cpp | 58 VRC = MRI->getRegClass(VR); in Initialize()
152 VRC, MRI, TII); in GetValueInMiddleOfBlock()
188 Loc, VRC, MRI, TII); in GetValueInMiddleOfBlock()
289 Updater->VRC, Updater->MRI, in GetUndefVal()
300 Updater->VRC, Updater->MRI, in CreateEmptyPHI()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | MachineSSAUpdater.cpp | 57 VRC = MRI->getRegClass(VR); in Initialize()
151 VRC, MRI, TII); in GetValueInMiddleOfBlock()
187 Loc, VRC, MRI, TII); in GetValueInMiddleOfBlock()
305 Updater->VRC, Updater->MRI, in GetUndefVal()
316 Updater->VRC, Updater->MRI, in CreateEmptyPHI()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | MachineSSAUpdater.cpp | 62 VRC = MRI->getRegClass(VR); in Initialize()
155 VRC, MRI, TII); in GetValueInMiddleOfBlock()
191 Loc, VRC, MRI, TII); in GetValueInMiddleOfBlock()
297 Updater->VRC, Updater->MRI, in GetUndefVal()
308 Updater->VRC, Updater->MRI, in CreateEmptyPHI()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineSSAUpdater.h | 47 const TargetRegisterClass *VRC; variable
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | MachineSSAUpdater.h | 46 const TargetRegisterClass *VRC; variable
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | MachineSSAUpdater.h | 46 const TargetRegisterClass *VRC; variable
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 1889 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC); in legalizeOpWithMove() local
1890 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC)) in legalizeOpWithMove()
1891 VRC = &AMDGPU::VReg_64RegClass; in legalizeOpWithMove()
1893 VRC = &AMDGPU::VGPR_32RegClass; in legalizeOpWithMove()
1895 unsigned Reg = MRI.createVirtualRegister(VRC); in legalizeOpWithMove()
2168 const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg); in readlaneVGPRToSGPR() local
2169 const TargetRegisterClass *SRC = RI.getEquivalentSGPRClass(VRC); in readlaneVGPRToSGPR()
2171 unsigned SubRegs = VRC->getSize() / 4; in readlaneVGPRToSGPR()
2231 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr; in legalizeOperands() local
2239 VRC = OpRC; in legalizeOperands()
[all …]
|
| D | SIRegisterInfo.h | 127 const TargetRegisterClass *VRC) const;
|
| D | SIRegisterInfo.cpp | 750 const TargetRegisterClass *VRC) const { in getEquivalentSGPRClass()
751 switch (VRC->getSize()) { in getEquivalentSGPRClass()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 3087 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC); in legalizeOpWithMove() local
3088 if (RI.getCommonSubClass(&AMDGPU::VReg_64RegClass, VRC)) in legalizeOpWithMove()
3089 VRC = &AMDGPU::VReg_64RegClass; in legalizeOpWithMove()
3091 VRC = &AMDGPU::VGPR_32RegClass; in legalizeOpWithMove()
3093 unsigned Reg = MRI.createVirtualRegister(VRC); in legalizeOpWithMove()
3401 const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg); in readlaneVGPRToSGPR() local
3402 const TargetRegisterClass *SRC = RI.getEquivalentSGPRClass(VRC); in readlaneVGPRToSGPR()
3404 unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32; in readlaneVGPRToSGPR()
3504 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr; in legalizeOperands() local
3512 VRC = OpRC; in legalizeOperands()
[all …]
|
| D | SIRegisterInfo.h | 159 const TargetRegisterClass *VRC) const;
|
| D | SIRegisterInfo.cpp | 1297 const TargetRegisterClass *VRC) const { in getEquivalentSGPRClass()
1298 switch (getRegSizeInBits(*VRC)) { in getEquivalentSGPRClass()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 402 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); in ConstrainForSubReg() local
403 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
407 if (RC && RC != VRC) in ConstrainForSubReg()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 446 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); in ConstrainForSubReg() local
447 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
451 if (RC && RC != VRC) in ConstrainForSubReg()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 469 const TargetRegisterClass *VRC = MRI->getRegClass(VReg); in ConstrainForSubReg() local
470 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
474 if (RC && RC != VRC) in ConstrainForSubReg()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | p9-instrs.txt | 393 [PO VRT VRA VRB VRC XO] vpermr
|
| /external/toolchain-utils/android_bench_suite/panorama_input/ |
| D | test_007.ppm | 1862 …"� #"' ����%!0.� �! � � MD<k_XmaZk[VRC=xia�~v{hdn[WbOOzfffYWeX…
|
| /external/cldr/tools/java/org/unicode/cldr/util/data/external/ |
| D | 2013-1_UNLOCODE_CodeListPart2.csv | 7110 ,"HR","VRC","Virovitica","Virovitica","10","-23-----","RL","0401",,"4549N 01723E",
15417 "�","IT","VRC","Verucchio","Verucchio","RN","--3-----","RL","1301",,"4359N 01225E","@Sta@Sub@Coo"
|
| D | 2013-1_UNLOCODE_CodeListPart1.csv | 8158 ,"BR","VRC","Vera Cruz","Vera Cruz","SP","--3-----","RQ","0607",,,
16256 ,"CZ","VRC","Vrchlab�","Vrchlabi",,"-23-----","AA","0212",,"5037N 01536E",
31296 ,"ES","VRC","Villar de Ca�as","Villar de Canas","CU","--3-----","RQ","1001",,"3947N 00233W",
43006 ,"FR","VRC","Varces-Alli�res-et-Risset","Varces-Allieres-et-Risset","38","--3-----","RL","0201",,,
|
| D | 2013-1_UNLOCODE_CodeListPart3.csv | 1256 ,"PH","VRC","Virac","Virac",,"---4----","AI","9401",,,
10649 ,"US","VRC","Beaver City","Beaver City","NE","--3-----","RQ","1001",,"4008N 09949W",
|