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Searched refs:VREG (Results 1 – 25 of 26) sorted by relevance

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/external/llvm/test/CodeGen/AMDGPU/
Dllvm.AMDGPU.bfe.i32.ll88 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
89 ; SI: buffer_store_dword [[VREG]],
183 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
184 ; SI: buffer_store_dword [[VREG]],
195 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
196 ; SI: buffer_store_dword [[VREG]],
207 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
208 ; SI: buffer_store_dword [[VREG]],
219 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], -1
220 ; SI: buffer_store_dword [[VREG]],
[all …]
Dllvm.AMDGPU.bfe.u32.ll195 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
196 ; SI: buffer_store_dword [[VREG]],
331 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
332 ; SI: buffer_store_dword [[VREG]],
343 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
344 ; SI: buffer_store_dword [[VREG]],
355 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
356 ; SI: buffer_store_dword [[VREG]],
367 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], 1
368 ; SI: buffer_store_dword [[VREG]],
[all …]
Dtrunc-store-i1.ll8 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
9 ; SI: buffer_store_byte [[VREG]],
27 ; SI: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
28 ; SI: buffer_store_byte [[VREG]],
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.ubfe.ll186 ; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
187 ; GCN: buffer_store_dword [[VREG]],
322 ; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
323 ; GCN: buffer_store_dword [[VREG]],
334 ; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
335 ; GCN: buffer_store_dword [[VREG]],
346 ; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
347 ; GCN: buffer_store_dword [[VREG]],
358 ; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], 1
359 ; GCN: buffer_store_dword [[VREG]],
[all …]
Dllvm.amdgcn.sbfe.ll78 ; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
79 ; GCN: buffer_store_dword [[VREG]],
173 ; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
174 ; GCN: buffer_store_dword [[VREG]],
184 ; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
185 ; GCN: buffer_store_dword [[VREG]],
195 ; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], 0
196 ; GCN: buffer_store_dword [[VREG]],
206 ; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], -1
207 ; GCN: buffer_store_dword [[VREG]],
[all …]
Dtrunc-store-i1.ll8 ; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
9 ; GCN: buffer_store_byte [[VREG]],
28 ; GCN: v_mov_b32_e32 [[VREG:v[0-9]+]], [[SREG]]
29 ; GCN: buffer_store_byte [[VREG]],
Di1-copy-from-loop.ll11 ; SI: v_cndmask_b32_e64 [[VREG:v[0-9]+]], 0, -1, [[SREG]]
14 ; SI-NOT: [[VREG]]
16 ; SI: v_cmp_ne_u32_e32 vcc, 0, [[VREG]]
Dtrunc.ll59 ; GCN: v_and_b32_e32 [[VREG:v[0-9]+]], 1, v{{[0-9]+}}
69 ; GCN: v_and_b32_e32 [[VREG:v[0-9]+]], 1, v{{[0-9]+}}
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dmemcpy_dereferenceable.ll6 ; CHECK: lxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
8 ; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
9 ; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
39 ; CHECK: lxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
41 ; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
42 ; CHECK: stxvd2x [[VREG:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
Dppc32-pic.ll21 ; SMALL-BSS-DAG: lwz [[VREG:[0-9]+]], bar@GOT(30)
22 ; SMALL-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]])
Dppc32-pic-large.ll26 ; LARGE-BSS-DAG: lwz [[VREG:[0-9]+]], [[VREF:\.LC[0-9]+]]-.LTOC(30)
27 ; LARGE-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]])
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/
DSDNodeDbgValue.h36 VREG = 3 ///< Value is a virtual register. enumerator
79 assert((Kind == VREG || Kind == FRAMEIX) && in SDDbgValue()
82 if (kind == VREG) in SDDbgValue()
110 unsigned getVReg() const { assert (kind==VREG); return u.VReg; } in getVReg()
DInstrEmitter.cpp727 } else if (SD->getKind() == SDDbgValue::VREG) { in EmitDbgValue()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dtail-dup-debugloc.ll7 ; CHECK: [[VREG:%[^ ]+]]:gr64 = COPY $rdi
8 ; CHECK: TEST64rr [[VREG]], [[VREG]]
/external/llvm/test/CodeGen/PowerPC/
Dppc32-pic.ll21 ; SMALL-BSS-DAG: lwz [[VREG:[0-9]+]], bar@GOT(30)
22 ; SMALL-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]])
Dppc32-pic-large.ll24 ; LARGE-BSS-DAG: lwz [[VREG:[0-9]+]], [[VREF:\.LC[0-9]+]]-.LTOC(30)
25 ; LARGE-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]])
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dvec-args-05.ll23 ; CHECK-STACK-DAG: vl [[VREG:%v[0-9]+]], 0([[REG1]])
24 ; CHECK-STACK-DAG: vst [[VREG]], 160(%r15)
/external/llvm/test/CodeGen/SystemZ/
Dvec-args-05.ll23 ; CHECK-STACK-DAG: vl [[VREG:%v[0-9]+]], 0([[REG1]])
24 ; CHECK-STACK-DAG: vst [[VREG]], 160(%r15)
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SimplifyCFG/
Dremove-debug-2.ll15 ; CHECK: [[VREG:%[^ ]+]] = select
16 ; CHECK: store i32 [[VREG]],{{.*}} !dbg [[storeLoc:![0-9]+]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dswp-prolog-phi.ll8 ; CHECK: vcmp.gt([[VREG:(v[0-9]+)]].uh,v{{[0-9]+}}.uh)
9 ; CHECK-NOT: vcmp.gt([[VREG]].uh,v{{[0-9]+}}.uh)
Dswp-epilog-phi7.ll9 ; CHECK: [[VREG:v([0-9]+)]]{{.*}} = {{.*}}vmem(r{{[0-9]+}}++#1)
13 ; CHECK: [[VREG1:v([0-9]+)]] = [[VREG]]
14 ; CHECK: [[VREG]] = v{{[0-9]+}}
16 ; CHECK: = vlalign([[VREG]],[[VREG1]],#1)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/GlobalISel/
Darm-instruction-select.mir107 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
112 ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg
136 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
141 ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, $noreg, $noreg
166 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
169 ; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]]
196 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
199 ; CHECK: [[VREGTRUNC:%[0-9]+]]:gprnopc = COPY [[VREG]]
226 ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY $r0
233 ; CHECK: $r0 = COPY [[VREG]]
[all …]
Darm-irtranslator.ll64 ; CHECK: [[VREG:%[0-9]+]]:_(s8) = G_TRUNC [[VREGR0]]
65 ; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_SEXT [[VREG]]
108 ; CHECK: [[VREG:%[0-9]+]]:_(s16) = G_TRUNC [[VREGR0]]
109 ; CHECK: [[VREGEXT:%[0-9]+]]:_(s32) = G_ZEXT [[VREG]]
/external/pdfium/third_party/libopenjpeg20/
Ddwt.c604 #define VREG __m256i macro
606 #define LOAD(x) _mm256_load_si256((const VREG*)(x))
607 #define LOADU(x) _mm256_loadu_si256((const VREG*)(x))
608 #define STORE(x,y) _mm256_store_si256((VREG*)(x),(y))
609 #define STOREU(x,y) _mm256_storeu_si256((VREG*)(x),(y))
614 #define VREG __m128i macro
616 #define LOAD(x) _mm_load_si128((const VREG*)(x))
617 #define LOADU(x) _mm_loadu_si128((const VREG*)(x))
618 #define STORE(x,y) _mm_store_si128((VREG*)(x),(y))
619 #define STOREU(x,y) _mm_storeu_si128((VREG*)(x),(y))
[all …]
/external/vixl/src/aarch64/
Doperands-aarch64.cc182 #define VREG(n) v##n, macro
183 const VRegister VRegister::vregisters[] = {AARCH64_REGISTER_CODE_LIST(VREG)};
184 #undef VREG

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