Searched refs:VZEXT (Results 1 – 8 of 8) sorted by relevance
/external/llvm/lib/Target/X86/ |
D | X86IntrinsicsInfo.h | 1141 X86ISD::VZEXT, 0), 1143 X86ISD::VZEXT, 0), 1145 X86ISD::VZEXT, 0), 1147 X86ISD::VZEXT, 0), 1149 X86ISD::VZEXT, 0), 1151 X86ISD::VZEXT, 0), 1153 X86ISD::VZEXT, 0), 1155 X86ISD::VZEXT, 0), 1157 X86ISD::VZEXT, 0), 1159 X86ISD::VZEXT, 0), [all …]
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D | X86ISelLowering.h | 286 VZEXT, enumerator
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D | X86InstrFragmentsSIMD.td | 120 def X86vzext : SDNode<"X86ISD::VZEXT",
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D | X86ISelLowering.cpp | 8106 InputV = DAG.getNode(X86ISD::VZEXT, DL, ExtVT, InputV); in lowerVectorShuffleAsSpecificZeroOrAnyExtend() 14006 return DAG.getNode(X86ISD::VZEXT, dl, VT, In); in LowerAVXExtend() 14034 return DAG.getNode(X86ISD::VZEXT, DL, VT, In); in LowerZERO_EXTEND_AVX512() 16031 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT) in LowerSIGN_EXTEND_AVX512() 19468 unsigned ExSSE41 = (ISD::MULHU == Opcode ? X86ISD::VZEXT : X86ISD::VSEXT); in LowerMULH() 22174 case X86ISD::VZEXT: return "X86ISD::VZEXT"; in getTargetNodeName() 30846 if (V != Op && V.getOpcode() == X86ISD::VZEXT) { in combineVZext() 30854 return DAG.getNode(X86ISD::VZEXT, DL, VT, V.getOperand(0)); in combineVZext() 30865 return DAG.getNode(X86ISD::VZEXT, DL, VT, DAG.getBitcast(OpVT, V)); in combineVZext() 30887 return DAG.getNode(X86ISD::VZEXT, DL, VT, Op); in combineVZext() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
D | X86ISelLowering.h | 299 VZEXT, enumerator
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D | X86InstrFragmentsSIMD.td | 106 def X86vzext : SDNode<"X86ISD::VZEXT",
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D | X86ISelLowering.cpp | 5414 assert((X86ISD::VSEXT == Opc || X86ISD::VZEXT == Opc) && "Unexpected opcode"); in getExtendInVec() 6337 case X86ISD::VZEXT: { in getFauxShuffleMask() 10455 InputV = getExtendInVec(X86ISD::VZEXT, DL, ExtVT, InputV, DAG); in lowerVectorShuffleAsSpecificZeroOrAnyExtend() 16914 return DAG.getNode(X86ISD::VZEXT, dl, VT, In); in LowerAVXExtend() 19276 X86ISD::VSEXT : X86ISD::VZEXT; in LowerEXTEND_VECTOR_INREG() 19602 SDValue Sext = getExtendInVec(X86ISD::VZEXT, dl, RegVT, SlicedVec, DAG); in LowerLoad() 25995 case X86ISD::VZEXT: return "X86ISD::VZEXT"; in getTargetNodeName() 28935 case X86ISD::VZEXT: { in computeKnownBitsForTargetNode() 29175 Shuffle = unsigned(X86ISD::VZEXT); in matchUnaryVectorShuffle() 39285 (Opcode == X86ISD::VZEXT) || (Opcode == ISD::ZERO_EXTEND_VECTOR_INREG); in combineVSZext() [all …]
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
D | X86GenFastISel.inc | 5281 // FastEmit functions for X86ISD::VZEXT. 5558 case X86ISD::VZEXT: return fastEmit_X86ISD_VZEXT_r(VT, RetVT, Op0, Op0IsKill);
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