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Searched refs:VecReg (Results 1 – 4 of 4) sorted by relevance

/external/llvm/lib/Target/AMDGPU/
DSILowerControlFlow.cpp112 std::pair<unsigned, int> computeIndirectRegAndOffset(unsigned VecReg,
599 SILowerControlFlow::computeIndirectRegAndOffset(unsigned VecReg, int Offset) const { in computeIndirectRegAndOffset() argument
600 unsigned SubReg = TRI->getSubReg(VecReg, AMDGPU::sub0); in computeIndirectRegAndOffset()
602 SubReg = VecReg; in computeIndirectRegAndOffset()
604 const TargetRegisterClass *SuperRC = TRI->getPhysRegClass(VecReg); in computeIndirectRegAndOffset()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp1249 unsigned VecReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
1252 assert(VecReg == MI.getOperand(1).getReg()); in expandPostRAPseudo()
1256 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef) in expandPostRAPseudo()
1258 .addReg(VecReg, RegState::ImplicitDefine) in expandPostRAPseudo()
1259 .addReg(VecReg, in expandPostRAPseudo()
DSIISelLowering.cpp2968 unsigned VecReg, in computeIndirectRegAndOffset() argument
/external/swiftshader/third_party/subzero/src/
DIceTargetLoweringX86BaseImpl.h5275 Variable *VecReg = nullptr;
5280 auto lowerSet = [this, &Base, SpreadValue, &VecReg](Type Ty,
5288 assert(VecReg != nullptr);
5289 _storep(VecReg, Mem);
5291 assert(VecReg != nullptr);
5292 _storeq(VecReg, Mem);
5309 VecReg = makeVectorOfZeros(IceType_v16i8);