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Searched refs:Vm (Results 1 – 25 of 217) sorted by relevance

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/external/v8/src/arm/
Ddisasm-arm.cc1899 int Vd, Vm, Vn; in DecodeSpecialCondition() local
1902 Vm = instr->VFPMRegValue(kDoublePrecision); in DecodeSpecialCondition()
1906 Vm = instr->VFPMRegValue(kSimd128Precision); in DecodeSpecialCondition()
1916 "vqadd.s%d q%d, q%d, q%d", size, Vd, Vn, Vm); in DecodeSpecialCondition()
1925 if (Vm == Vn) { in DecodeSpecialCondition()
1928 "vmov q%d, q%d", Vd, Vm); in DecodeSpecialCondition()
1932 "vorr q%d, q%d, q%d", Vd, Vn, Vm); in DecodeSpecialCondition()
1938 "vand q%d, q%d, q%d", Vd, Vn, Vm); in DecodeSpecialCondition()
1949 "vqsub.s%d q%d, q%d, q%d", size, Vd, Vn, Vm); in DecodeSpecialCondition()
1960 op, size, Vd, Vn, Vm); in DecodeSpecialCondition()
[all …]
Dsimulator-arm.cc3945 void Widen(Simulator* simulator, int Vd, int Vm) { in Widen() argument
3949 simulator->get_neon_register<T, kDoubleSize>(Vm, src); in Widen()
3957 void Abs(Simulator* simulator, int Vd, int Vm) { in Abs() argument
3960 simulator->get_neon_register<T, SIZE>(Vm, src); in Abs()
3968 void Neg(Simulator* simulator, int Vd, int Vm) { in Neg() argument
3971 simulator->get_neon_register<T, SIZE>(Vm, src); in Neg()
3979 void SaturatingNarrow(Simulator* simulator, int Vd, int Vm) { in SaturatingNarrow() argument
3983 simulator->get_neon_register(Vm, src); in SaturatingNarrow()
3991 void AddSaturate(Simulator* simulator, int Vd, int Vm, int Vn) { in AddSaturate() argument
3995 simulator->get_neon_register(Vm, src2); in AddSaturate()
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenDAGISel.inc1201 /* 2550*/ OPC_RecordChild0, // #2 = $Vm
1225 …2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vd), (and:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, (xor:{ *:[v2i32] } …
1226 … // Dst: (VBSLd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
1233 …1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vd), (and:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, (xor:{ *:[v1i64] } …
1234 … // Dst: (VBSLd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vd, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
1247 …4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vd), (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, (xor:{ *:[v4i32] } …
1248 … // Dst: (VBSLq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
1255 …2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vd), (and:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, (xor:{ *:[v2i64] } …
1256 … // Dst: (VBSLq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vd, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
1280 …2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vd), (and:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, (xor:{ *:[v2i32] } …
[all …]
DARMGenGlobalISel.inc1389 … *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VADDv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:…
1393 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // Vm
1419 …[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, D…
1424 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1444 …[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, D…
1449 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1469 …$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i3…
1474 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
1494 …$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i3…
1499 GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
[all …]
DARMGenMCCodeEmitter.inc5779 // op: Vm
5803 // op: Vm
5825 // op: Vm
5849 // op: Vm
5879 // op: Vm
5909 // op: Vm
5939 // op: Vm
5961 // op: Vm
5991 // op: Vm
6007 // op: Vm
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrNEON.td2528 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2529 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2534 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2535 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2543 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2544 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2550 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2551 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2557 : N2Vnp<op19_18, op17_16, op10_8, op7, 0, (outs DPR:$Vd), (ins DPR:$Vm),
2559 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
[all …]
DARMInstrFormats.td2207 bits<5> Vm;
2211 let Inst{3-0} = Vm{3-0};
2212 let Inst{5} = Vm{4};
2220 OpcodeStr, Dt, "$Vd, $Vm", "", pattern> {
2222 bits<5> Vm;
2227 let Inst{5} = Vm{4};
2228 let Inst{3-0} = Vm{3-0};
2260 bits<5> Vm;
2264 let Inst{3-0} = Vm{3-0};
2265 let Inst{5} = Vm{4};
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td2437 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2438 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2443 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2444 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2452 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2453 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2459 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2460 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2466 : N2Vnp<op19_18, op17_16, op10_8, op7, 0, (outs DPR:$Vd), (ins DPR:$Vm),
2468 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
[all …]
DARMInstrFormats.td2175 bits<5> Vm;
2179 let Inst{3-0} = Vm{3-0};
2180 let Inst{5} = Vm{4};
2188 OpcodeStr, Dt, "$Vd, $Vm", "", pattern> {
2190 bits<5> Vm;
2195 let Inst{5} = Vm{4};
2196 let Inst{3-0} = Vm{3-0};
2228 bits<5> Vm;
2232 let Inst{3-0} = Vm{3-0};
2233 let Inst{5} = Vm{4};
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td1818 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
1819 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
1824 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
1825 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
1833 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1834 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
1840 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1841 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
1849 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
1850 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
[all …]
DARMInstrFormats.td1733 bits<5> Vm;
1737 let Inst{3-0} = Vm{3-0};
1738 let Inst{5} = Vm{4};
1757 bits<5> Vm;
1761 let Inst{3-0} = Vm{3-0};
1762 let Inst{5} = Vm{4};
1779 bits<5> Vm;
1784 let Inst{3-0} = Vm{3-0};
1785 let Inst{5} = Vm{4};
1813 bits<5> Vm;
[all …]
/external/javasqlite/src/main/java/SQLite/
DDatabase.java307 Vm vm = compile(sql); in get_table()
360 Vm vm = compile(sql, args); in get_table()
414 Vm vm = compile(sql, args); in get_table()
680 public Vm compile(String sql) throws SQLite.Exception { in compile()
682 Vm vm = new Vm(); in compile()
697 public Vm compile(String sql, String args[]) throws SQLite.Exception { in compile()
699 Vm vm = new Vm(); in compile()
753 private native void vm_compile(String sql, Vm vm) in vm_compile()
763 private native void vm_compile_args(String sql, Vm vm, String args[]) in vm_compile_args()
DVm.java7 public class Vm { class
/external/honggfuzz/examples/apache-httpd/corpus_http2/
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/external/honggfuzz/examples/apache-httpd/corpus_http1/
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td6812 : I<(outs vectype:$Vd), (ins listtype:$Vn, vectype:$Vm), asm,
6813 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "", []>,
6817 bits<5> Vm;
6821 let Inst{20-16} = Vm;
6833 : I<(outs vectype:$dst), (ins vectype:$Vd, listtype:$Vn, vectype:$Vm), asm,
6834 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "$Vd = $dst", []>,
6838 bits<5> Vm;
6842 let Inst{20-16} = Vm;
10042 : BaseCryptoV82<(outs V128:$Vd), (ins V128:$Vn, V128:$Vm), asm, asmops,
10043 "$Vm = $Vd", []> {
[all …]
/external/capstone/arch/ARM/
DARMDisassembler.c5003 unsigned Vm, imm, cmode, op; in DecodeVCVTD() local
5006 Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); in DecodeVCVTD()
5007 Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); in DecodeVCVTD()
5023 if (!Check(&S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) in DecodeVCVTD()
5034 unsigned Vm, imm, cmode, op; in DecodeVCVTQ() local
5037 Vm = (fieldFromInstruction_4(Insn, 0, 4) << 0); in DecodeVCVTQ()
5038 Vm |= (fieldFromInstruction_4(Insn, 5, 1) << 4); in DecodeVCVTQ()
5054 if (!Check(&S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) in DecodeVCVTQ()
/external/python/httplib2/python2/httplib2/test/
Dserver.key126 BbCePaf74sd4Jfffygju7E/NGjwDQeyRxVBwSwIDAQABAoIBAQCtAYO4fd39q/Vm
/external/ImageMagick/PerlMagick/t/reference/write/filter/
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