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Searched refs:Vn (Results 1 – 25 of 334) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
D	ARMGenGlobalISel.inc	1389 …add:{ :[v1i64] } DPR:{ :[v1i64] }:$Vn, DPR:{ :[v1i64] }:$Vm) => (VADDv1i64:{ :[v1i64] } DPR:… 1392 GIR_Copy, /NewInsnID/0, /OldInsnID/0, /OpIdx/1, // Vn 1419 …[v2i32] }:$Vn, DPR:{ :[v2i32] }:$Vm), DPR:{ :[v2i32] }:$src1) => (VABAsv2i32:{ :[v2i32] } DPR… 1423 GIR_Copy, /NewInsnID/0, /OldInsnID/1, /OpIdx/2, // Vn 1444 …[v2i32] }:$Vn, DPR:{ :[v2i32] }:$Vm), DPR:{ :[v2i32] }:$src1) => (VABAuv2i32:{ :[v2i32] } DPR… 1448 GIR_Copy, /NewInsnID/0, /OldInsnID/1, /OpIdx/2, // Vn 1469 …] }, DPR:{ :[v2i32] }:$Vn, DPR:{ :[v2i32] }:$Vm)) => (VABAsv2i32:{ :[v2i32] } DPR:{ :[v2i32]… 1473 GIR_Copy, /NewInsnID/0, /OldInsnID/1, /OpIdx/2, // Vn 1494 …] }, DPR:{ :[v2i32] }:$Vn, DPR:{ :[v2i32] }:$Vm)) => (VABAuv2i32:{ :[v2i32] } DPR:{ :[v2i32]… 1498 GIR_Copy, /NewInsnID/0, /OldInsnID/1, /OpIdx/2, // Vn [all …]
D	ARMGenDAGISel.inc	1194 /* 2537/ OPC_RecordChild0, // #0 = $Vn 1225 …// Src: (or:{ :[v2i32] } (and:{ :[v2i32] } DPR:{ :[v2i32] }:$Vn, DPR:{ :[v2i32] }:$Vd), (and:{… 1226 … // Dst: (VBSLd:{ :[v2i32] } DPR:{ :[v2i32] }:$Vd, DPR:{ :[v2i32] }:$Vn, DPR:{ :[v2i32] }:$Vm) 1233 …// Src: (or:{ :[v1i64] } (and:{ :[v1i64] } DPR:{ :[v1i64] }:$Vn, DPR:{ :[v1i64] }:$Vd), (and:{… 1234 … // Dst: (VBSLd:{ :[v1i64] } DPR:{ :[v1i64] }:$Vd, DPR:{ :[v1i64] }:$Vn, DPR:{ :[v1i64] }:$Vm) 1247 …// Src: (or:{ :[v4i32] } (and:{ :[v4i32] } QPR:{ :[v4i32] }:$Vn, QPR:{ :[v4i32] }:$Vd), (and:{… 1248 … // Dst: (VBSLq:{ :[v4i32] } QPR:{ :[v4i32] }:$Vd, QPR:{ :[v4i32] }:$Vn, QPR:{ :[v4i32] }:$Vm) 1255 …// Src: (or:{ :[v2i64] } (and:{ :[v2i64] } QPR:{ :[v2i64] }:$Vn, QPR:{ :[v2i64] }:$Vd), (and:{… 1256 … // Dst: (VBSLq:{ :[v2i64] } QPR:{ :[v2i64] }:$Vd, QPR:{ :[v2i64] }:$Vn, QPR:{ :[v2i64] }:$Vm) 1280 …// Src: (or:{ :[v2i32] } (and:{ :[v2i32] } DPR:{ :[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vd), (and:{… [all …]
/external/v8/src/arm/
D	disasm-arm.cc	1899 int Vd, Vm, Vn; in DecodeSpecialCondition() local 1903 Vn = instr->VFPNRegValue(kDoublePrecision); in DecodeSpecialCondition() 1907 Vn = instr->VFPNRegValue(kSimd128Precision); in DecodeSpecialCondition() 1916 "vqadd.s%d q%d, q%d, q%d", size, Vd, Vn, Vm); in DecodeSpecialCondition() 1925 if (Vm == Vn) { in DecodeSpecialCondition() 1932 "vorr q%d, q%d, q%d", Vd, Vn, Vm); in DecodeSpecialCondition() 1938 "vand q%d, q%d, q%d", Vd, Vn, Vm); in DecodeSpecialCondition() 1949 "vqsub.s%d q%d, q%d, q%d", size, Vd, Vn, Vm); in DecodeSpecialCondition() 1960 op, size, Vd, Vn, Vm); in DecodeSpecialCondition() 1968 op, size, Vd, Vn, Vm); in DecodeSpecialCondition() [all …]
D	simulator-arm.cc	3991 void AddSaturate(Simulator* simulator, int Vd, int Vm, int Vn) { in AddSaturate() argument 3994 simulator->get_neon_register(Vn, src1); in AddSaturate() 4003 void SubSaturate(Simulator* simulator, int Vd, int Vm, int Vn) { in SubSaturate() argument 4006 simulator->get_neon_register(Vn, src1); in SubSaturate() 4063 void Test(Simulator* simulator, int Vd, int Vm, int Vn) { in Test() argument 4066 simulator->get_neon_register<T, SIZE>(Vn, src1); in Test() 4075 void Add(Simulator* simulator, int Vd, int Vm, int Vn) { in Add() argument 4078 simulator->get_neon_register<T, SIZE>(Vn, src1); in Add() 4087 void Sub(Simulator* simulator, int Vd, int Vm, int Vn) { in Sub() argument 4090 simulator->get_neon_register<T, SIZE>(Vn, src1); in Sub() [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
D	ARMInstrNEON.td	2640 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, 2641 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", 2642 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> { 2644 let TwoOperandAliasConstraint = "$Vn = $Vd"; 2653 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, 2654 OpcodeStr, "$Vd, $Vn, $Vm", "", 2655 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{ 2657 let TwoOperandAliasConstraint = "$Vn = $Vd"; 2665 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), 2666 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", [all …]
D	ARMInstrFormats.td	`2314 bits<5> Vn; 2319 let Inst{19-16} = Vn{3-0}; 2320 let Inst{7} = Vn{4}; 2329 Dt, "$Vd, $Vn, $Vm", "", pattern> { 2331 bits<5> Vn; 2337 let Inst{19-16} = Vn{3-0}; 2338 let Inst{7} = Vn{4}; 2359 bits<5> Vn; 2365 let Inst{19-16} = Vn{3-0}; 2366 let Inst{7} = Vn{4}; [all …]`
/external/llvm/lib/Target/ARM/
D	ARMInstrNEON.td	2549 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, 2550 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", 2551 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> { 2553 let TwoOperandAliasConstraint = "$Vn = $Vd"; 2562 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, 2563 OpcodeStr, "$Vd, $Vn, $Vm", "", 2564 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{ 2566 let TwoOperandAliasConstraint = "$Vn = $Vd"; 2574 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), 2575 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", [all …]
D	ARMInstrFormats.td	`2282 bits<5> Vn; 2287 let Inst{19-16} = Vn{3-0}; 2288 let Inst{7} = Vn{4}; 2297 Dt, "$Vd, $Vn, $Vm", "", pattern> { 2299 bits<5> Vn; 2305 let Inst{19-16} = Vn{3-0}; 2306 let Inst{7} = Vn{4}; 2327 bits<5> Vn; 2333 let Inst{19-16} = Vn{3-0}; 2334 let Inst{7} = Vn{4}; [all …]`
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
D	ARMInstrNEON.td	1896 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, 1897 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", 1898 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> { 1907 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, 1908 OpcodeStr, "$Vd, $Vn, $Vm", "", 1909 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{ 1917 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane), 1918 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "", 1920 (Ty (ShOp (Ty DPR:$Vn), 1927 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane), [all …]
D	ARMInstrFormats.td	`1812 bits<5> Vn; 1817 let Inst{19-16} = Vn{3-0}; 1818 let Inst{7} = Vn{4}; 1832 bits<5> Vn; 1838 let Inst{19-16} = Vn{3-0}; 1839 let Inst{7} = Vn{4}; 1853 bits<5> Vn; 1859 let Inst{19-16} = Vn{3-0}; 1860 let Inst{7} = Vn{4}; 1881 bits<5> Vn; [all …]`
/external/honggfuzz/examples/apache-httpd/corpus_http1/
D	42ee40ca6c14930cc605046aacae7c07.0000d69e.honggfuzz.cov	12 …�q��8e�Tlc]�VW��$�n��j\|[�F��%؄�]?��z�V�6\�&�JL�+��~��_�R�3��X�Vn��V�� bo��쇘�gn�\… 24 …�q��8e�Tlc]�VW��$�n��j\|[�F��%؄�]?��z�V�6\�&�JL�+��~��_�R�3��X�Vn��V�� bo��쇘�gn�\… 48 …�q��8e�Tlc]�VW��$�n��j\|[�F��%؄�]?��z�V�6\�&�JL�+��~��_�R�3��X�Vn��V�� bo��쇘�gn�\… 57 …�q��8e�Tlc]�VW��$�n��j\|[�F��%؄�]?��z�V�6\�&�JL�+��~��_�R�3��X�Vn��V�� bo��쇘�gn�\… 69 …�q��8e�Tlc]�VW��$�n��j\|[�F��%؄�]?��z�V�6\�&�JL�+��~��_�R�3��X�Vn��V�� bo��쇘�gn�\… 93 …�q��8e�Tlc]�VW��$�n��j\|[�F��%؄�]?��z�V�6\�&�JL�+��~��_�R�3��X�Vn��V�� bo��쇘�gn�\… 104 …�q��8e�Tlc]�VW��$�n��j\|[�F��%؄�]?��z�V�6\�&�JL�+��~��_�R�3��X�Vn��V�� bo��쇘�gn�\… 128 …�q��8e�Tlc]�VW��$�n��j\|[�F��%؄�]?��z�V�6\�&�JL�+��~��_�R�3��X�Vn��V�� bo��쇘�gn�\… 137 …�q��8e�Tlc]�VW��$�n��j\|[�F��%؄�]?��z�V�6\�&�JL�+��~��_�R�3��X�Vn��V�� bo��쇘�gn�\… 149 …�q��8e�Tlc]�VW��$�n��j\|[�F��%؄�]?��z�V�6\�&�JL�+��~��_�R�3��X�Vn��V�� bo��쇘�gn�\… [all …]
D	1de3fef346798b78cfe693c8f16ca014.0000292e.honggfuzz.cov	`15 D��8[�xًLe�Vn�+�$طKs�1��^?GT�`
D	a21709d07b594a21c3f44b5b90f4e7dd.0000ba5b.honggfuzz.cov	`14 …�=��%:�#^��\|��J��<]��e� j�3�S��?�%��Pa.g<~��T��گ=��X2�߽��g��E�)�p��T^H�[{3:L�VnY��2� 45 …�=��%:�#^��\|��J��<]��e� j�3�S��?�%��Pa.g<~��T��گ=��X2�߽��g��E�)�p��T^H�[{3:L�VnY��2�`
/external/honggfuzz/examples/apache-httpd/corpus_http2/
D	42ee40ca6c14930cc605046aacae7c07.0000d69e.honggfuzz.cov	12 …�q��8e�Tlc]�VW��$�n��j\|[�F��%؄�]?��z�V�6\�&�JL�+��~��_�R�3��X�Vn��V�� bo��쇘�gn�\… 24 …�q��8e�Tlc]�VW��$�n��j\|[�F��%؄�]?��z�V�6\�&�JL�+��~��_�R�3��X�Vn��V�� bo��쇘�gn�\… 48 …�q��8e�Tlc]�VW��$�n��j\|[�F��%؄�]?��z�V�6\�&�JL�+��~��_�R�3��X�Vn��V�� bo��쇘�gn�\… 57 …�q��8e�Tlc]�VW��$�n��j\|[�F��%؄�]?��z�V�6\�&�JL�+��~��_�R�3��X�Vn��V�� bo��쇘�gn�\… 69 …�q��8e�Tlc]�VW��$�n��j\|[�F��%؄�]?��z�V�6\�&�JL�+��~��_�R�3��X�Vn��V�� bo��쇘�gn�\… 93 …�q��8e�Tlc]�VW��$�n��j\|[�F��%؄�]?��z�V�6\�&�JL�+��~��_�R�3��X�Vn��V�� bo��쇘�gn�\… 104 …�q��8e�Tlc]�VW��$�n��j\|[�F��%؄�]?��z�V�6\�&�JL�+��~��_�R�3��X�Vn��V�� bo��쇘�gn�\… 128 …�q��8e�Tlc]�VW��$�n��j\|[�F��%؄�]?��z�V�6\�&�JL�+��~��_�R�3��X�Vn��V�� bo��쇘�gn�\… 137 …�q��8e�Tlc]�VW��$�n��j\|[�F��%؄�]?��z�V�6\�&�JL�+��~��_�R�3��X�Vn��V�� bo��쇘�gn�\… 149 …�q��8e�Tlc]�VW��$�n��j\|[�F��%؄�]?��z�V�6\�&�JL�+��~��_�R�3��X�Vn��V�� bo��쇘�gn�\… [all …]
D	1de3fef346798b78cfe693c8f16ca014.0000292e.honggfuzz.cov	`15 D��8[�xًLe�Vn�+�$طKs�1��^?GT�`
D	a21709d07b594a21c3f44b5b90f4e7dd.0000ba5b.honggfuzz.cov	`14 …�=��%:�#^��\|��J��<]��e� j�3�S��?�%��Pa.g<~��T��گ=��X2�߽��g��E�)�p��T^H�[{3:L�VnY��2� 45 …�=��%:�#^��\|��J��<]��e� j�3�S��?�%��Pa.g<~��T��گ=��X2�߽��g��E�)�p��T^H�[{3:L�VnY��2�`
D	944b47f95ce08f8f55a291c2939c9331.000011a6.honggfuzz.cov	`44 …�_�]�@a]z�=䊳ށ:ϒ%��'��a�!>��"��ߪ�/�7fo={�]~U��¬rK��NW�vj�L��Vn��d��k��.��J�@…`
/external/ImageMagick/PerlMagick/t/reference/read/
D	input_gif.miff	`15 …jhdKibSieVd{GgwWpeTumQjeg{xhlorXX�\^�f\�rp�yw�mr�]f�sx�]�=]�Gd�Ik�Jm�Sp�Ls�Vn�Xt�fw�t{�ho�mw�W\|�f~…`
D	input_bmp.miff	`16 …jhdKibSieVd{GgwWpeTumQjeg{xhlorXX�\^�f\�rp�yw�mr�]f�sx�]�=]�Gd�Ik�Jm�Sp�Ls�Vn�Xt�fw�t{�ho�mw�W\|�f~…`
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
D	AArch64InstrFormats.td	5521 def : InstAlias<asm # "\t$Vd.4h, $Vn.4h, #0", 5522 (!cast<Instruction>(NAME # v4i16rz) V64:$Vd, V64:$Vn), 0>; 5523 def : InstAlias<asm # "\t$Vd.8h, $Vn.8h, #0", 5524 (!cast<Instruction>(NAME # v8i16rz) V128:$Vd, V128:$Vn), 0>; 5526 def : InstAlias<asm # "\t$Vd.2s, $Vn.2s, #0", 5527 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>; 5528 def : InstAlias<asm # "\t$Vd.4s, $Vn.4s, #0", 5529 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>; 5530 def : InstAlias<asm # "\t$Vd.2d, $Vn.2d, #0", 5531 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>; [all …]
D	AArch64InstrInfo.td	3113 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b\|.8b $Vd, $Vn}", 3114 (NOTv8i8 V64:$Vd, V64:$Vn)>; 3115 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b\|.16b $Vd, $Vn}", 3116 (NOTv16i8 V128:$Vd, V128:$Vn)>; 4581 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm 4586 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm 5910 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))), 5911 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 5912 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))), 5913 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; [all …]
/external/ImageMagick/PerlMagick/t/reference/filter/
D	Shave.miff	`15 …<3�;3�61�>9�<7�8/�D9�?4�))�++�2,�2%�<(�:*�7-�LH�C@�9$�9(�>2�QI�E>�NI�QS�Ta�Vn�No�Ux�Wo�Zi�We�OT��…`
D	Colorize.miff	`15 …2�!2��0�I/�O2�L,�M,�O/�R.�S+�V1�P4�>+�'�( �)!�)"�) �(!�-1�<M�>]�5Z�=k�Vn�q[�yR�tV�[I�=2�64�,-…`
/external/llvm/lib/Target/AArch64/
D	AArch64InstrInfo.td	2849 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b\|.8b $Vd, $Vn}", 2850 (NOTv8i8 V64:$Vd, V64:$Vn)>; 2851 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b\|.16b $Vd, $Vn}", 2852 (NOTv16i8 V128:$Vd, V128:$Vn)>; 4250 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm 4255 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm 5517 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))), 5518 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; 5519 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))), 5520 (COPY_TO_REGCLASS V64:$Vn, GPR64)>; [all …]
/external/ImageMagick/PerlMagick/t/reference/write/read/
D	input_bmp.miff	`42 …jhdKibSieVd{GgwWpeTumQjeg{xhlorXX�\^�f\�rp�yw�mr�]f�sx�]�=]�Gd�Ik�Jm�Sp�Ls�Vn�Xt�fw�t{�ho�mw�W\|�f~…`

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