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Searched refs:WL_PHY_REG (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_training_leveling.c996 DDR_PHY_DATA, WL_PHY_REG(0), reg_data); in ddr3_tip_dynamic_write_leveling()
1112 WL_PHY_REG(effective_cs), in ddr3_tip_dynamic_write_leveling()
1327 DDR_PHY_DATA, WL_PHY_REG(effective_cs), &data)); in ddr3_tip_wl_supp_align_phase_shift()
1339 WL_PHY_REG(effective_cs), write_data); in ddr3_tip_wl_supp_align_phase_shift()
1351 WL_PHY_REG(effective_cs), write_data); in ddr3_tip_wl_supp_align_phase_shift()
1363 WL_PHY_REG(effective_cs), write_data); in ddr3_tip_wl_supp_align_phase_shift()
1375 WL_PHY_REG(effective_cs), write_data); in ddr3_tip_wl_supp_align_phase_shift()
1384 WL_PHY_REG(effective_cs), data); in ddr3_tip_wl_supp_align_phase_shift()
Dmv_ddr_regs.h384 #define WL_PHY_REG(cs) (WL_PHY_BASE + (cs) * 0x4) macro
Dddr3_debug.c594 WL_PHY_REG(csindex), in ddr3_tip_print_stability_log()
1480 reg = (direction == 0) ? WL_PHY_REG(cs) : RL_PHY_REG(cs); in ddr3_tip_run_leveling_sweep_test()
Dddr3_training.c2019 WL_PHY_REG(effective_cs), in ddr3_tip_ddr3_reset_phy_regs()