Home
last modified time | relevance | path

Searched refs:WR_LVL_PH_SEL_OFFS (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dmv_ddr_regs.h385 #define WR_LVL_PH_SEL_OFFS 6 macro
Dddr3_training_leveling.c1100 temp = (reg_data >> WR_LVL_PH_SEL_OFFS) & WR_LVL_PH_SEL_PHASE1; in ddr3_tip_dynamic_write_leveling()
1101 reg_data &= ~(WR_LVL_PH_SEL_MASK << WR_LVL_PH_SEL_OFFS); in ddr3_tip_dynamic_write_leveling()
1102 reg_data |= (temp << WR_LVL_PH_SEL_OFFS); in ddr3_tip_dynamic_write_leveling()