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Searched refs:WR_LVL_PH_SEL_PHASE1 (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dmv_ddr_regs.h387 #define WR_LVL_PH_SEL_PHASE1 1 macro
Dddr3_training_leveling.c1100 temp = (reg_data >> WR_LVL_PH_SEL_OFFS) & WR_LVL_PH_SEL_PHASE1; in ddr3_tip_dynamic_write_leveling()