Searched refs:Width1 (Results 1 – 5 of 5) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 800 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT); in LowerSHLParts() local
802 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift); in LowerSHLParts()
838 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT); in LowerSRXParts() local
840 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift); in LowerSRXParts()
855 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero; in LowerSRXParts()
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| D | SIInstrInfo.cpp | 2131 unsigned Width1 = (*MIb.memoperands_begin())->getSize(); in checkInstOffsetsDoNotOverlap() local
2133 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) { in checkInstOffsetsDoNotOverlap()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 976 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT); in LowerSHLParts() local
978 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift); in LowerSHLParts()
1014 SDValue Width1 = DAG.getConstant(VT.getSizeInBits() - 1, DL, VT); in LowerSRXParts() local
1016 SDValue CompShift = DAG.getNode(ISD::SUB, DL, VT, Width1, Shift); in LowerSRXParts()
1031 SDValue HiBig = SRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, Width1) : Zero; in LowerSRXParts()
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| D | SIInstrInfo.cpp | 1354 unsigned Width1 = (*MIb.memoperands_begin())->getSize(); in checkInstOffsetsDoNotOverlap() local
1356 offsetsDoNotOverlap(Width0, Offset0, Width1, Offset1)) { in checkInstOffsetsDoNotOverlap()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 3929 SDValue Width1 = DAG.getNode(ISD::SUB, dl, ShVT, in ExpandNode() local
3932 SDValue And0 = DAG.getNode(ISD::AND, dl, ShVT, Op1, Width1); in ExpandNode()
3933 SDValue And1 = DAG.getNode(ISD::AND, dl, ShVT, NegOp1, Width1); in ExpandNode()
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