| /external/pcre/dist2/doc/ |
| D | pcre2-config.txt | 27 --prefix Writes the directory prefix used in the PCRE2 installation
32 Writes the directory prefix used in the PCRE2 installation
36 --version Writes the version number of the installed PCRE2 libraries to
39 --libs8 Writes to the standard output the command line options
43 --libs16 Writes to the standard output the command line options
47 --libs32 Writes to the standard output the command line options
52 Writes to the standard output the command line options
56 --cflags Writes to the standard output the command line options
61 Writes to the standard output the command line options
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| /external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-mca/ |
| D | RegisterFile.cpp | 245 void RegisterFile::collectWrites(SmallVectorImpl<WriteRef> &Writes, in collectWrites() argument
252 Writes.push_back(WR); in collectWrites()
258 Writes.push_back(WR); in collectWrites()
262 llvm::sort(Writes.begin(), Writes.end(), in collectWrites()
266 auto It = std::unique(Writes.begin(), Writes.end()); in collectWrites()
267 Writes.resize(std::distance(Writes.begin(), It)); in collectWrites()
270 for (const WriteRef &WR : Writes) { in collectWrites()
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| D | InstrBuilder.cpp | 184 ID.Writes.resize(TotalDefs); in populateWrites()
195 WriteDescriptor &Write = ID.Writes[CurrentDef]; in populateWrites()
225 WriteDescriptor &Write = ID.Writes[Index]; in populateWrites()
261 WriteDescriptor &Write = ID.Writes[TotalDefs - 1]; in populateWrites()
435 if (D.Writes.empty()) in createInstruction()
440 APInt WriteMask(D.Writes.size(), 0); in createInstruction()
452 for (const WriteDescriptor &WD : D.Writes) { in createInstruction()
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| D | Instruction.h | 188 void setDependentWrites(unsigned Writes) { in setDependentWrites() argument
189 DependentWrites = Writes; in setDependentWrites()
190 IsReady = !Writes; in setDependentWrites()
256 std::vector<WriteDescriptor> Writes; // Implicit writes are at the end. member
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| D | RegisterFile.h | 159 void collectWrites(llvm::SmallVectorImpl<WriteRef> &Writes,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleA57.td | 80 list <SchedWriteRes> Writes = writes;
532 SchedVar<A57LMAddrPred1, A57LDMOpsListNoregin.Writes[0-1]>,
533 SchedVar<A57LMAddrPred2, A57LDMOpsListNoregin.Writes[0-3]>,
534 SchedVar<A57LMAddrPred3, A57LDMOpsListNoregin.Writes[0-5]>,
535 SchedVar<A57LMAddrPred4, A57LDMOpsListNoregin.Writes[0-7]>,
536 SchedVar<A57LMAddrPred5, A57LDMOpsListNoregin.Writes[0-9]>,
537 SchedVar<A57LMAddrPred6, A57LDMOpsListNoregin.Writes[0-11]>,
538 SchedVar<A57LMAddrPred7, A57LDMOpsListNoregin.Writes[0-13]>,
539 SchedVar<A57LMAddrPred8, A57LDMOpsListNoregin.Writes[0-15]>,
540 SchedVar<NoSchedPred, A57LDMOpsListNoregin.Writes[0-15]>
[all …]
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| D | ARMParallelDSP.cpp | 495 Instructions &Writes) { in AliasCandidates() argument
500 Writes.push_back(&I); in AliasCandidates()
508 Instructions &Writes, OpChainList &MACCandidates) { in AreAliased() argument
521 for (auto *I : Writes) { in AreAliased()
618 Instructions Reads, Writes; in MatchSMLAD() local
619 AliasCandidates(Header, Reads, Writes); in MatchSMLAD()
622 if (AreAliased(AA, Reads, Writes, R.MACCandidates)) in MatchSMLAD()
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| D | ARMScheduleA9.td | 1883 list <WriteSequence> Writes = writes;
2111 SchedVar<A9LMAdr1Pred, A9WriteLMOpsList.Writes[0-1]>,
2112 SchedVar<A9LMAdr2Pred, A9WriteLMOpsList.Writes[0-3]>,
2113 SchedVar<A9LMAdr3Pred, A9WriteLMOpsList.Writes[0-5]>,
2114 SchedVar<A9LMAdr4Pred, A9WriteLMOpsList.Writes[0-7]>,
2115 SchedVar<A9LMAdr5Pred, A9WriteLMOpsList.Writes[0-9]>,
2116 SchedVar<A9LMAdr6Pred, A9WriteLMOpsList.Writes[0-11]>,
2117 SchedVar<A9LMAdr7Pred, A9WriteLMOpsList.Writes[0-13]>,
2118 SchedVar<A9LMAdr8Pred, A9WriteLMOpsList.Writes[0-15]>,
2216 SchedVar<A9LMAdr1Pred, A9WriteLMfpPostRAOpsList.Writes[0-0, 8-8]>,
[all …]
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| /external/llvm/utils/TableGen/ |
| D | CodeGenSchedule.cpp | 383 IdxVec &Writes, IdxVec &Reads) const { in findRWs() argument
387 findRWs(WriteDefs, Writes, false); in findRWs()
509 IdxVec Writes, Reads; in collectSchedClasses() local
511 findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads); in collectSchedClasses()
516 unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, ProcIndices); in collectSchedClasses()
551 if (!SC.Writes.empty()) { in collectSchedClasses()
554 for (IdxIter WI = SC.Writes.begin(), WE = SC.Writes.end(); WI != WE; ++WI) in collectSchedClasses()
567 IdxVec Writes; in collectSchedClasses() local
570 Writes, Reads); in collectSchedClasses()
571 for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI) in collectSchedClasses()
[all …]
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| D | CodeGenSchedule.h | 132 IdxVec Writes; member
148 return ItinClassDef == IC && makeArrayRef(Writes) == W && in isKeyEqual()
370 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
382 unsigned findSchedClassIdx(Record *ItinClassDef, ArrayRef<unsigned> Writes,
432 void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads,
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| D | SubtargetEmitter.cpp | 852 IdxVec Writes = SC.Writes; in GenSchedClassTables() local
866 Writes.clear(); in GenSchedClassTables()
869 Writes, Reads); in GenSchedClassTables()
872 if (Writes.empty()) { in GenSchedClassTables()
879 Writes, Reads); in GenSchedClassTables()
883 if (Writes.empty()) { in GenSchedClassTables()
893 for (unsigned W : Writes) { in GenSchedClassTables()
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | CodeGenSchedule.cpp | 494 IdxVec &Writes, IdxVec &Reads) const { in findRWs() argument
498 findRWs(WriteDefs, Writes, false); in findRWs()
612 IdxVec Writes, Reads; in collectSchedClasses() local
614 findRWs(Inst->TheDef->getValueAsListOfDefs("SchedRW"), Writes, Reads); in collectSchedClasses()
617 unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads, /*ProcIndices*/{0}); in collectSchedClasses()
658 if (!SC.Writes.empty()) { in collectSchedClasses()
662 for (IdxIter WI = SC.Writes.begin(), WE = SC.Writes.end(); WI != WE; in collectSchedClasses()
677 IdxVec Writes; in collectSchedClasses() local
680 Writes, Reads); in collectSchedClasses()
682 for (unsigned WIdx : Writes) in collectSchedClasses()
[all …]
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| D | CodeGenSchedule.h | 130 IdxVec Writes; member
148 return ItinClassDef == IC && makeArrayRef(Writes) == W && in isKeyEqual()
418 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
485 void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads,
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| D | SubtargetEmitter.cpp | 1032 IdxVec Writes = SC.Writes; in GenSchedClassTables() local
1046 Writes.clear(); in GenSchedClassTables()
1049 Writes, Reads); in GenSchedClassTables()
1052 if (Writes.empty()) { in GenSchedClassTables()
1058 Writes, Reads); in GenSchedClassTables()
1062 if (Writes.empty()) { in GenSchedClassTables()
1073 for (unsigned W : Writes) { in GenSchedClassTables()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/MC/ |
| D | MCInstrAnalysis.cpp | 22 APInt &Writes) const { in clearsSuperRegisters()
23 Writes.clearAllBits(); in clearsSuperRegisters()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/ |
| D | IntrinsicsARM.td | 97 // Writes to the GE bits.
104 // Writes to the GE bits.
107 // Writes to the GE bits.
118 // Writes to the GE bits.
138 // Writes to the GE bits.
141 // Writes to the GE bits.
152 // Writes to the GE bits.
155 // Writes to the GE bits.
158 // Writes to the GE bits.
161 // Writes to the GE bits.
[all …]
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| /external/blktrace/doc/ |
| D | blktrace.tex | 163 Reads Queued: 0, 0KiB Writes Queued: 7, 128KiB
165 Reads Completed: 0, 0KiB Writes Completed: 11, 168KiB
170 Reads Queued: 0, 0KiB Writes Queued: 1, 28KiB
172 Reads Completed: 0, 0KiB Writes Completed: 0, 0KiB
177 Reads Queued: 0, 0KiB Writes Queued: 11, 168KiB
179 Reads Completed: 0, 0KiB Writes Completed: 11, 168KiB
299 Reads Queued: 0, 0KiB Writes Queued: 9, 5,520KiB
301 Reads Completed: 0, 0KiB Writes Completed: 0, 0KiB
305 Reads Queued: 2,411, 38,576KiB Writes Queued: 769, 425,408KiB
307 Reads Completed: 0, 0KiB Writes Completed: 0, 0KiB
[all …]
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| /external/tensorflow/tensorflow/core/api_def/base_api/ |
| D | api_def_WriteFile.pbtxt | 15 summary: "Writes contents to the file at input filename. Creates file and recursively"
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| D | api_def_ExperimentalDatasetToTFRecord.pbtxt | 23 summary: "Writes the given dataset to the given file using the TFRecord format."
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| /external/flatbuffers/dart/lib/ |
| D | flat_buffers.dart | 100 /// Writes the data in this helper to the [Builder].
360 /// Writes a Float64 to the tail of the buffer after preparing space for it.
368 /// Writes a Float32 to the tail of the buffer after preparing space for it.
376 /// Writes a Int64 to the tail of the buffer after preparing space for it.
384 /// Writes a Uint32 to the tail of the buffer after preparing space for it.
392 /// Writes a Uint16 to the tail of the buffer after preparing space for it.
400 /// Writes a Uint8 to the tail of the buffer after preparing space for it.
408 /// Writes a Uint64 to the tail of the buffer after preparing space for it.
416 /// Writes a Uint32 to the tail of the buffer after preparing space for it.
424 /// Writes a Uint16 to the tail of the buffer after preparing space for it.
[all …]
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| /external/swiftshader/third_party/LLVM/bindings/ocaml/bitwriter/ |
| D | llvm_bitwriter.ml | 16 (* Writes the bitcode for module the given path. Returns true if successful. *)
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | InlineSpiller.cpp | 866 bool Reads, Writes; in reMaterializeFor() local
868 tie(Reads, Writes) = MI->readsWritesVirtualRegister(VirtReg.reg, &Ops); in reMaterializeFor()
869 if (Writes) { in reMaterializeFor()
1126 bool Reads, Writes; in spillAroundUses() local
1128 tie(Reads, Writes) = MI->readsWritesVirtualRegister(Reg, &Ops); in spillAroundUses()
1146 if (Writes) { in spillAroundUses()
1190 if (Writes) { in spillAroundUses()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| D | MCInstrAnalysis.h | 88 APInt &Writes) const;
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| /external/grpc-grpc/doc/ |
| D | status_ordering.md | 5 1. Reads and Writes Must not succeed after Status has been delivered.
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| /external/perfetto/test/configs/ |
| D | long_trace.cfg | 10 # Writes the userspace buffer into the file every 2.5 seconds.
|