1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Xtensa processor core configuration information. 4 * This file is autogenerated, please do not edit. 5 * 6 * Copyright (C) 1999-2015 Tensilica Inc. 7 */ 8 9 #ifndef _XTENSA_CORE_CONFIGURATION_H 10 #define _XTENSA_CORE_CONFIGURATION_H 11 12 13 /**************************************************************************** 14 Parameters Useful for Any Code, USER or PRIVILEGED 15 ****************************************************************************/ 16 17 /* 18 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is 19 * configured, and a value of 0 otherwise. These macros are always defined. 20 */ 21 22 23 /*---------------------------------------------------------------------- 24 ISA 25 ----------------------------------------------------------------------*/ 26 27 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ 28 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ 29 #define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ 30 #define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ 31 #define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ 32 #define XCHAL_HAVE_DEBUG 1 /* debug option */ 33 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ 34 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ 35 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ 36 #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ 37 #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ 38 #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ 39 #define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ 40 #define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ 41 #define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ 42 #define XCHAL_HAVE_MUL32 1 /* MULL instruction */ 43 #define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ 44 #define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ 45 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ 46 #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ 47 #define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ 48 #define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ 49 #define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ 50 #define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ 51 #define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ 52 #define XCHAL_HAVE_ABS 1 /* ABS instruction */ 53 /*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ 54 /*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ 55 #define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ 56 #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ 57 #define XCHAL_HAVE_SPECULATION 0 /* speculation */ 58 #define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ 59 #define XCHAL_NUM_CONTEXTS 1 /* */ 60 #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ 61 #define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ 62 #define XCHAL_HAVE_PRID 1 /* processor ID register */ 63 #define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ 64 #define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ 65 #define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ 66 #define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ 67 #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ 68 #define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ 69 #define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ 70 #define XCHAL_HAVE_THREADPTR 0 /* THREADPTR register */ 71 #define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */ 72 #define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */ 73 #define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one */ 74 #define XCHAL_HAVE_MAC16 1 /* MAC16 package */ 75 76 #define XCHAL_HAVE_FUSION 0 /* Fusion*/ 77 #define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ 78 #define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ 79 #define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ 80 #define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ 81 #define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ 82 #define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ 83 #define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ 84 #define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ 85 #define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ 86 #define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ 87 #define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ 88 #define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ 89 #define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ 90 #define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ 91 #define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ 92 #define XCHAL_HAVE_HIFI_MINI 0 93 94 95 #define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */ 96 #define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ 97 #define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */ 98 #define XCHAL_HAVE_FP 0 /* single prec floating point */ 99 #define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */ 100 #define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */ 101 #define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */ 102 #define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */ 103 #define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ 104 #define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ 105 #define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ 106 #define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ 107 #define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ 108 #define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ 109 #define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ 110 111 #define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ 112 #define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ 113 #define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ 114 #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ 115 #define XCHAL_HAVE_PDX4 0 /* PDX4 */ 116 #define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ 117 #define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ 118 #define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ 119 #define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ 120 #define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ 121 #define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ 122 #define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ 123 #define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ 124 #define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ 125 #define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ 126 #define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ 127 #define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ 128 #define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ 129 #define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ 130 #define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */ 131 #define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ 132 133 134 /*---------------------------------------------------------------------- 135 MISC 136 ----------------------------------------------------------------------*/ 137 138 #define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ 139 #define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ 140 #define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ 141 #define XCHAL_DATA_WIDTH 4 /* data width in bytes */ 142 #define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay 143 (1 = 5-stage, 2 = 7-stage) */ 144 #define XCHAL_CLOCK_GATING_GLOBAL 0 /* global clock gating */ 145 #define XCHAL_CLOCK_GATING_FUNCUNIT 0 /* funct. unit clock gating */ 146 /* In T1050, applies to selected core load and store instructions (see ISA): */ 147 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ 148 #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ 149 #define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ 150 #define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ 151 152 #define XCHAL_SW_VERSION 1100002 /* sw version of this header */ 153 154 #define XCHAL_CORE_ID "de212" /* alphanum core name 155 (CoreID) set in the Xtensa 156 Processor Generator */ 157 158 #define XCHAL_BUILD_UNIQUE_ID 0x0005A985 /* 22-bit sw build ID */ 159 160 /* 161 * These definitions describe the hardware targeted by this software. 162 */ 163 #define XCHAL_HW_CONFIGID0 0xC283DFFE /* ConfigID hi 32 bits*/ 164 #define XCHAL_HW_CONFIGID1 0x1C85A985 /* ConfigID lo 32 bits*/ 165 #define XCHAL_HW_VERSION_NAME "LX6.0.2" /* full version name */ 166 #define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */ 167 #define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */ 168 #define XCHAL_HW_VERSION 260002 /* major*100+minor */ 169 #define XCHAL_HW_REL_LX6 1 170 #define XCHAL_HW_REL_LX6_0 1 171 #define XCHAL_HW_REL_LX6_0_2 1 172 #define XCHAL_HW_CONFIGID_RELIABLE 1 173 /* If software targets a *range* of hardware versions, these are the bounds: */ 174 #define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */ 175 #define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */ 176 #define XCHAL_HW_MIN_VERSION 260002 /* earliest targeted hw */ 177 #define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */ 178 #define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */ 179 #define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */ 180 181 182 /*---------------------------------------------------------------------- 183 CACHE 184 ----------------------------------------------------------------------*/ 185 186 #define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ 187 #define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ 188 #define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ 189 #define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ 190 191 #define XCHAL_ICACHE_SIZE 8192 /* I-cache size in bytes or 0 */ 192 #define XCHAL_DCACHE_SIZE 8192 /* D-cache size in bytes or 0 */ 193 194 #define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ 195 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ 196 197 #define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ 198 #define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ 199 #define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ 200 #define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ 201 #define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ 202 #define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ 203 #define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ 204 #define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ 205 #define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ 206 #define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ 207 208 209 210 211 /**************************************************************************** 212 Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code 213 ****************************************************************************/ 214 215 216 #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY 217 218 /*---------------------------------------------------------------------- 219 CACHE 220 ----------------------------------------------------------------------*/ 221 222 #define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ 223 224 /* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ 225 226 /* Number of cache sets in log2(lines per way): */ 227 #define XCHAL_ICACHE_SETWIDTH 7 228 #define XCHAL_DCACHE_SETWIDTH 7 229 230 /* Cache set associativity (number of ways): */ 231 #define XCHAL_ICACHE_WAYS 2 232 #define XCHAL_DCACHE_WAYS 2 233 234 /* Cache features: */ 235 #define XCHAL_ICACHE_LINE_LOCKABLE 1 236 #define XCHAL_DCACHE_LINE_LOCKABLE 1 237 #define XCHAL_ICACHE_ECC_PARITY 0 238 #define XCHAL_DCACHE_ECC_PARITY 0 239 240 /* Cache access size in bytes (affects operation of SICW instruction): */ 241 #define XCHAL_ICACHE_ACCESS_SIZE 4 242 #define XCHAL_DCACHE_ACCESS_SIZE 4 243 244 #define XCHAL_DCACHE_BANKS 1 /* number of banks */ 245 246 /* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ 247 #define XCHAL_CA_BITS 4 248 249 /* Whether MEMCTL register has anything useful */ 250 #define XCHAL_USE_MEMCTL (((XCHAL_LOOP_BUFFER_SIZE > 0) || \ 251 XCHAL_DCACHE_IS_COHERENT || \ 252 XCHAL_HAVE_ICACHE_DYN_WAYS || \ 253 XCHAL_HAVE_DCACHE_DYN_WAYS) && \ 254 (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0)) 255 256 257 /*---------------------------------------------------------------------- 258 INTERNAL I/D RAM/ROMs and XLMI 259 ----------------------------------------------------------------------*/ 260 261 #define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ 262 #define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */ 263 #define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ 264 #define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */ 265 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ 266 #define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */ 267 268 /* Instruction RAM 0: */ 269 #define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */ 270 #define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */ 271 #define XCHAL_INSTRAM0_SIZE 131072 /* size in bytes */ 272 #define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ 273 274 /* Data RAM 0: */ 275 #define XCHAL_DATARAM0_VADDR 0x3FFE0000 /* virtual address */ 276 #define XCHAL_DATARAM0_PADDR 0x3FFE0000 /* physical address */ 277 #define XCHAL_DATARAM0_SIZE 131072 /* size in bytes */ 278 #define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ 279 #define XCHAL_DATARAM0_BANKS 1 /* number of banks */ 280 281 /* XLMI Port 0: */ 282 #define XCHAL_XLMI0_VADDR 0x3FFC0000 /* virtual address */ 283 #define XCHAL_XLMI0_PADDR 0x3FFC0000 /* physical address */ 284 #define XCHAL_XLMI0_SIZE 131072 /* size in bytes */ 285 #define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */ 286 287 #define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ 288 289 290 /*---------------------------------------------------------------------- 291 INTERRUPTS and TIMERS 292 ----------------------------------------------------------------------*/ 293 294 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ 295 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ 296 #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ 297 #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ 298 #define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ 299 #define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */ 300 #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ 301 #define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */ 302 #define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels 303 (not including level zero) */ 304 #define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ 305 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ 306 307 /* Masks of interrupts at each interrupt level: */ 308 #define XCHAL_INTLEVEL1_MASK 0x001F80FF 309 #define XCHAL_INTLEVEL2_MASK 0x00000100 310 #define XCHAL_INTLEVEL3_MASK 0x00200E00 311 #define XCHAL_INTLEVEL4_MASK 0x00001000 312 #define XCHAL_INTLEVEL5_MASK 0x00002000 313 #define XCHAL_INTLEVEL6_MASK 0x00000000 314 #define XCHAL_INTLEVEL7_MASK 0x00004000 315 316 /* Masks of interrupts at each range 1..n of interrupt levels: */ 317 #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF 318 #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF 319 #define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF 320 #define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF 321 #define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF 322 #define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF 323 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF 324 325 /* Level of each interrupt: */ 326 #define XCHAL_INT0_LEVEL 1 327 #define XCHAL_INT1_LEVEL 1 328 #define XCHAL_INT2_LEVEL 1 329 #define XCHAL_INT3_LEVEL 1 330 #define XCHAL_INT4_LEVEL 1 331 #define XCHAL_INT5_LEVEL 1 332 #define XCHAL_INT6_LEVEL 1 333 #define XCHAL_INT7_LEVEL 1 334 #define XCHAL_INT8_LEVEL 2 335 #define XCHAL_INT9_LEVEL 3 336 #define XCHAL_INT10_LEVEL 3 337 #define XCHAL_INT11_LEVEL 3 338 #define XCHAL_INT12_LEVEL 4 339 #define XCHAL_INT13_LEVEL 5 340 #define XCHAL_INT14_LEVEL 7 341 #define XCHAL_INT15_LEVEL 1 342 #define XCHAL_INT16_LEVEL 1 343 #define XCHAL_INT17_LEVEL 1 344 #define XCHAL_INT18_LEVEL 1 345 #define XCHAL_INT19_LEVEL 1 346 #define XCHAL_INT20_LEVEL 1 347 #define XCHAL_INT21_LEVEL 3 348 #define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ 349 #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ 350 #define XCHAL_NMILEVEL 7 /* NMI "level" (for use with 351 EXCSAVE/EPS/EPC_n, RFI n) */ 352 353 /* Type of each interrupt: */ 354 #define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 355 #define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 356 #define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 357 #define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 358 #define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 359 #define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 360 #define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER 361 #define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE 362 #define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 363 #define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 364 #define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER 365 #define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE 366 #define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 367 #define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER 368 #define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI 369 #define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE 370 #define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE 371 #define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE 372 #define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE 373 #define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE 374 #define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE 375 #define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE 376 377 /* Masks of interrupts for each type of interrupt: */ 378 #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000 379 #define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880 380 #define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000 381 #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F 382 #define XCHAL_INTTYPE_MASK_TIMER 0x00002440 383 #define XCHAL_INTTYPE_MASK_NMI 0x00004000 384 #define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 385 #define XCHAL_INTTYPE_MASK_PROFILING 0x00000000 386 387 /* Interrupt numbers assigned to specific interrupt sources: */ 388 #define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ 389 #define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */ 390 #define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */ 391 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED 392 #define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ 393 394 /* Interrupt numbers for levels at which only one interrupt is configured: */ 395 #define XCHAL_INTLEVEL2_NUM 8 396 #define XCHAL_INTLEVEL4_NUM 12 397 #define XCHAL_INTLEVEL5_NUM 13 398 #define XCHAL_INTLEVEL7_NUM 14 399 /* (There are many interrupts each at level(s) 1, 3.) */ 400 401 402 /* 403 * External interrupt mapping. 404 * These macros describe how Xtensa processor interrupt numbers 405 * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) 406 * map to external BInterrupt<n> pins, for those interrupts 407 * configured as external (level-triggered, edge-triggered, or NMI). 408 * See the Xtensa processor databook for more details. 409 */ 410 411 /* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ 412 #define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ 413 #define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ 414 #define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ 415 #define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ 416 #define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ 417 #define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ 418 #define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ 419 #define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */ 420 #define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */ 421 #define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */ 422 #define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */ 423 #define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */ 424 #define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ 425 #define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ 426 #define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */ 427 #define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */ 428 #define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */ 429 /* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ 430 #define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ 431 #define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ 432 #define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ 433 #define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ 434 #define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ 435 #define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ 436 #define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */ 437 #define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */ 438 #define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */ 439 #define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */ 440 #define XCHAL_INT15_EXTNUM 10 /* (intlevel 1) */ 441 #define XCHAL_INT16_EXTNUM 11 /* (intlevel 1) */ 442 #define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */ 443 #define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */ 444 #define XCHAL_INT19_EXTNUM 14 /* (intlevel 1) */ 445 #define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */ 446 #define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */ 447 448 449 /*---------------------------------------------------------------------- 450 EXCEPTIONS and VECTORS 451 ----------------------------------------------------------------------*/ 452 453 #define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture 454 number: 1 == XEA1 (old) 455 2 == XEA2 (new) 456 0 == XEAX (extern) or TX */ 457 #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ 458 #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ 459 #define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ 460 #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ 461 #define XCHAL_HAVE_HALT 0 /* halt architecture option */ 462 #define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ 463 #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ 464 #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ 465 #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ 466 #define XCHAL_VECBASE_RESET_VADDR 0x60000000 /* VECBASE reset value */ 467 #define XCHAL_VECBASE_RESET_PADDR 0x60000000 468 #define XCHAL_RESET_VECBASE_OVERLAP 0 469 470 #define XCHAL_RESET_VECTOR0_VADDR 0x50000000 471 #define XCHAL_RESET_VECTOR0_PADDR 0x50000000 472 #define XCHAL_RESET_VECTOR1_VADDR 0x40000400 473 #define XCHAL_RESET_VECTOR1_PADDR 0x40000400 474 #define XCHAL_RESET_VECTOR_VADDR 0x50000000 475 #define XCHAL_RESET_VECTOR_PADDR 0x50000000 476 #define XCHAL_USER_VECOFS 0x00000340 477 #define XCHAL_USER_VECTOR_VADDR 0x60000340 478 #define XCHAL_USER_VECTOR_PADDR 0x60000340 479 #define XCHAL_KERNEL_VECOFS 0x00000300 480 #define XCHAL_KERNEL_VECTOR_VADDR 0x60000300 481 #define XCHAL_KERNEL_VECTOR_PADDR 0x60000300 482 #define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 483 #define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x600003C0 484 #define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x600003C0 485 #define XCHAL_WINDOW_OF4_VECOFS 0x00000000 486 #define XCHAL_WINDOW_UF4_VECOFS 0x00000040 487 #define XCHAL_WINDOW_OF8_VECOFS 0x00000080 488 #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 489 #define XCHAL_WINDOW_OF12_VECOFS 0x00000100 490 #define XCHAL_WINDOW_UF12_VECOFS 0x00000140 491 #define XCHAL_WINDOW_VECTORS_VADDR 0x60000000 492 #define XCHAL_WINDOW_VECTORS_PADDR 0x60000000 493 #define XCHAL_INTLEVEL2_VECOFS 0x00000180 494 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0x60000180 495 #define XCHAL_INTLEVEL2_VECTOR_PADDR 0x60000180 496 #define XCHAL_INTLEVEL3_VECOFS 0x000001C0 497 #define XCHAL_INTLEVEL3_VECTOR_VADDR 0x600001C0 498 #define XCHAL_INTLEVEL3_VECTOR_PADDR 0x600001C0 499 #define XCHAL_INTLEVEL4_VECOFS 0x00000200 500 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x60000200 501 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x60000200 502 #define XCHAL_INTLEVEL5_VECOFS 0x00000240 503 #define XCHAL_INTLEVEL5_VECTOR_VADDR 0x60000240 504 #define XCHAL_INTLEVEL5_VECTOR_PADDR 0x60000240 505 #define XCHAL_INTLEVEL6_VECOFS 0x00000280 506 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0x60000280 507 #define XCHAL_INTLEVEL6_VECTOR_PADDR 0x60000280 508 #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS 509 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR 510 #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR 511 #define XCHAL_NMI_VECOFS 0x000002C0 512 #define XCHAL_NMI_VECTOR_VADDR 0x600002C0 513 #define XCHAL_NMI_VECTOR_PADDR 0x600002C0 514 #define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS 515 #define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR 516 #define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR 517 518 519 /*---------------------------------------------------------------------- 520 DEBUG MODULE 521 ----------------------------------------------------------------------*/ 522 523 /* Misc */ 524 #define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ 525 #define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */ 526 #define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ 527 528 /* On-Chip Debug (OCD) */ 529 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ 530 #define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ 531 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ 532 #define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ 533 #define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ 534 535 /* TRAX (in core) */ 536 #define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ 537 #define XCHAL_TRAX_MEM_SIZE 262144 /* TRAX memory size in bytes */ 538 #define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ 539 #define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ 540 #define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ 541 542 /* Perf counters */ 543 #define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */ 544 545 546 /*---------------------------------------------------------------------- 547 MMU 548 ----------------------------------------------------------------------*/ 549 550 /* See core-matmap.h header file for more details. */ 551 552 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ 553 #define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ 554 #define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ 555 #define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ 556 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ 557 #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ 558 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ 559 #define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table 560 [autorefill] and protection) 561 usable for an MMU-based OS */ 562 /* If none of the above last 4 are set, it's a custom TLB configuration. */ 563 564 #define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ 565 #define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ 566 #define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ 567 568 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ 569 570 571 #endif /* _XTENSA_CORE_CONFIGURATION_H */ 572 573