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Searched refs:XLenVT (Results 1 – 8 of 8) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVISelLowering.cpp46 MVT XLenVT = Subtarget.getXLenVT(); in RISCVTargetLowering() local
49 addRegisterClass(XLenVT, &RISCV::GPRRegClass); in RISCVTargetLowering()
62 setLoadExtAction(N, XLenVT, MVT::i1, Promote); in RISCVTargetLowering()
65 setOperationAction(ISD::DYNAMIC_STACKALLOC, XLenVT, Expand); in RISCVTargetLowering()
68 setOperationAction(ISD::BR_CC, XLenVT, Expand); in RISCVTargetLowering()
69 setOperationAction(ISD::SELECT, XLenVT, Custom); in RISCVTargetLowering()
70 setOperationAction(ISD::SELECT_CC, XLenVT, Expand); in RISCVTargetLowering()
84 setOperationAction(ISD::MUL, XLenVT, Expand); in RISCVTargetLowering()
85 setOperationAction(ISD::MULHS, XLenVT, Expand); in RISCVTargetLowering()
86 setOperationAction(ISD::MULHU, XLenVT, Expand); in RISCVTargetLowering()
[all …]
DRISCVInstrInfoC.td22 def uimmlog2xlennonzero : Operand<XLenVT>, ImmLeaf<XLenVT, [{
40 def simm6 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<6>(Imm);}]> {
52 def simm6nonzero : Operand<XLenVT>,
53 ImmLeaf<XLenVT, [{return (Imm != 0) && isInt<6>(Imm);}]> {
77 def c_lui_imm : Operand<XLenVT>,
78 ImmLeaf<XLenVT, [{return (Imm != 0) &&
94 def uimm7_lsb00 : Operand<XLenVT>,
95 ImmLeaf<XLenVT, [{return isShiftedUInt<5, 2>(Imm);}]> {
108 def uimm8_lsb00 : Operand<XLenVT>,
109 ImmLeaf<XLenVT, [{return isShiftedUInt<6, 2>(Imm);}]> {
[all …]
DRISCVISelDAGToDAG.cpp70 MVT XLenVT = Subtarget->getXLenVT(); in Select() local
82 if (Opcode == ISD::Constant && VT == XLenVT) { in Select()
88 RISCV::X0, XLenVT); in Select()
95 SDValue Imm = CurDAG->getTargetConstant(0, DL, XLenVT); in Select()
DRISCVRegisterInfo.td87 def XLenVT : ValueTypeByHwMode<[RV32, RV64, DefaultMode],
92 def GPR : RegisterClass<"RISCV", [XLenVT], 32, (add
107 def GPRNoX0 : RegisterClass<"RISCV", [XLenVT], 32, (add
120 def GPRNoX0X2 : RegisterClass<"RISCV", [XLenVT], 32, (add
133 def GPRC : RegisterClass<"RISCV", [XLenVT], 32, (add
145 def GPRTC : RegisterClass<"RISCV", [XLenVT], 32, (add
155 def SP : RegisterClass<"RISCV", [XLenVT], 32, (add X2)> {
DRISCVSubtarget.h41 MVT XLenVT = MVT::i32; variable
82 MVT getXLenVT() const { return XLenVT; } in getXLenVT()
DRISCVInstrInfo.td20 def SDT_RISCVCall : SDTypeProfile<0, -1, [SDTCisVT<0, XLenVT>]>;
81 def fencearg : Operand<XLenVT> {
93 def uimmlog2xlen : Operand<XLenVT>, ImmLeaf<XLenVT, [{
111 def uimm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]> {
116 def simm12 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<12>(Imm);}]> {
128 def uimm12 : Operand<XLenVT> {
146 def uimm20 : Operand<XLenVT> {
178 def bare_symbol : Operand<XLenVT> {
186 def ixlenimm : Operand<XLenVT> {
191 def simm32 : ImmLeaf<XLenVT, [{return isInt<32>(Imm);}]>;
[all …]
DRISCVSubtarget.cpp38 XLenVT = MVT::i64; in initializeSubtargetDependencies()
DRISCVInstrInfoF.td27 def frmarg : Operand<XLenVT> {