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/external/swiftshader/third_party/llvm-7.0/llvm/test/Instrumentation/MemorySanitizer/
Dmanual-shadow.ll5 … -msan -msan-shadow-base 3735928559 -msan-xor-mask 48879 -S | FileCheck --check-prefix=CHECK-XOR %s
6 …28559 -msan-xor-mask 48879 -msan-and-mask 4294901760 -S | FileCheck --check-prefix=CHECK-XOR-AND %s
27 ; CHECK-XOR-LABEL: @read_value
28 ; CHECK-XOR-NOT: ret i32
29 ; CHECK-XOR: xor{{.*}}48879
30 ; CHECK-XOR-NEXT: add{{.*}}3735928559
31 ; CHECK-XOR: ret i32
33 ; CHECK-XOR-AND-LABEL: @read_value
34 ; CHECK-XOR-AND-NOT: ret i32
35 ; CHECK-XOR-AND: and{{.*}}-4294901761
[all …]
/external/openssh/openbsd-compat/
Dchacha_private.h41 #define XOR(v,w) ((v) ^ (w)) macro
46 a = PLUS(a,b); d = ROTATE(XOR(d,a),16); \
47 c = PLUS(c,d); b = ROTATE(XOR(b,c),12); \
48 a = PLUS(a,b); d = ROTATE(XOR(d,a), 8); \
49 c = PLUS(c,d); b = ROTATE(XOR(b,c), 7);
167 x0 = XOR(x0,U8TO32_LITTLE(m + 0)); in chacha_encrypt_bytes()
168 x1 = XOR(x1,U8TO32_LITTLE(m + 4)); in chacha_encrypt_bytes()
169 x2 = XOR(x2,U8TO32_LITTLE(m + 8)); in chacha_encrypt_bytes()
170 x3 = XOR(x3,U8TO32_LITTLE(m + 12)); in chacha_encrypt_bytes()
171 x4 = XOR(x4,U8TO32_LITTLE(m + 16)); in chacha_encrypt_bytes()
[all …]
/external/openssh/
Dchacha.c42 #define XOR(v,w) ((v) ^ (w)) macro
47 a = PLUS(a,b); d = ROTATE(XOR(d,a),16); \
48 c = PLUS(c,d); b = ROTATE(XOR(b,c),12); \
49 a = PLUS(a,b); d = ROTATE(XOR(d,a), 8); \
50 c = PLUS(c,d); b = ROTATE(XOR(b,c), 7);
167 x0 = XOR(x0,U8TO32_LITTLE(m + 0)); in chacha_encrypt_bytes()
168 x1 = XOR(x1,U8TO32_LITTLE(m + 4)); in chacha_encrypt_bytes()
169 x2 = XOR(x2,U8TO32_LITTLE(m + 8)); in chacha_encrypt_bytes()
170 x3 = XOR(x3,U8TO32_LITTLE(m + 12)); in chacha_encrypt_bytes()
171 x4 = XOR(x4,U8TO32_LITTLE(m + 16)); in chacha_encrypt_bytes()
[all …]
/external/mesa3d/src/gallium/drivers/swr/rasterizer/jitter/
Dblend_jit.cpp321 result[0] = XOR(OR(src[0], dst[0]), VIMMED1(0xFFFFFFFF)); in LogicOpFunc()
322 result[1] = XOR(OR(src[1], dst[1]), VIMMED1(0xFFFFFFFF)); in LogicOpFunc()
323 result[2] = XOR(OR(src[2], dst[2]), VIMMED1(0xFFFFFFFF)); in LogicOpFunc()
324 result[3] = XOR(OR(src[3], dst[3]), VIMMED1(0xFFFFFFFF)); in LogicOpFunc()
330 result[0] = AND(XOR(src[0], VIMMED1(0xFFFFFFFF)), dst[0]); in LogicOpFunc()
331 result[1] = AND(XOR(src[1], VIMMED1(0xFFFFFFFF)), dst[1]); in LogicOpFunc()
332 result[2] = AND(XOR(src[2], VIMMED1(0xFFFFFFFF)), dst[2]); in LogicOpFunc()
333 result[3] = AND(XOR(src[3], VIMMED1(0xFFFFFFFF)), dst[3]); in LogicOpFunc()
338 result[0] = XOR(src[0], VIMMED1(0xFFFFFFFF)); in LogicOpFunc()
339 result[1] = XOR(src[1], VIMMED1(0xFFFFFFFF)); in LogicOpFunc()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dor-xor.ll191 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
192 ; CHECK-NEXT: ret i32 [[XOR]]
204 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
205 ; CHECK-NEXT: ret i32 [[XOR]]
218 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
219 ; CHECK-NEXT: ret i32 [[XOR]]
231 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[X:%.*]], [[Y:%.*]]
232 ; CHECK-NEXT: ret i32 [[XOR]]
245 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[TMP1]], [[B:%.*]]
246 ; CHECK-NEXT: ret i32 [[XOR]]
[all …]
Dand-or-not.ll297 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
298 ; CHECK-NEXT: ret i32 [[XOR]]
310 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
311 ; CHECK-NEXT: ret i32 [[XOR]]
323 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
324 ; CHECK-NEXT: ret i32 [[XOR]]
336 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[B:%.*]], [[A:%.*]]
337 ; CHECK-NEXT: ret i32 [[XOR]]
354 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A]], [[B]]
355 ; CHECK-NEXT: ret i32 [[XOR]]
[all …]
Dxor2.ll65 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 %val1, 1234
68 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[XOR1]], [[XOR]]
86 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 %x, 1234
88 ; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHR]], [[XOR]]
102 ; CHECK-NEXT: [[XOR:%.*]] = or i32 [[B_NOT]], %a
103 ; CHECK-NEXT: ret i32 [[XOR]]
115 ; CHECK-NEXT: [[XOR:%.*]] = or i32 [[B_NOT]], %a
116 ; CHECK-NEXT: ret i32 [[XOR]]
261 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[TMP1]], -1
262 ; CHECK-NEXT: ret i32 [[XOR]]
[all …]
Dselect-with-bitwise-ops.ll38 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 2
39 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]
96 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 8
97 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]
154 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 4096
155 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32 [[Y]]
210 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 4096
211 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[Y]], i32 [[XOR]]
312 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[Y:%.*]], 32
313 ; CHECK-NEXT: [[SELECT:%.*]] = select i1 [[CMP]], i32 [[XOR]], i32 [[Y]]
[all …]
Dxor.ll483 ; CHECK-NEXT: [[XOR:%.*]] = and i32 [[TMP1]], [[A:%.*]]
484 ; CHECK-NEXT: ret i32 [[XOR]]
494 ; CHECK-NEXT: [[XOR:%.*]] = and i32 [[TMP1]], [[A:%.*]]
495 ; CHECK-NEXT: ret i32 [[XOR]]
505 ; CHECK-NEXT: [[XOR:%.*]] = and i32 [[TMP1]], [[A:%.*]]
506 ; CHECK-NEXT: ret i32 [[XOR]]
516 ; CHECK-NEXT: [[XOR:%.*]] = and i32 [[TMP1]], [[A:%.*]]
517 ; CHECK-NEXT: ret i32 [[XOR]]
527 ; CHECK-NEXT: [[XOR:%.*]] = and i32 [[TMP1]], [[B:%.*]]
528 ; CHECK-NEXT: ret i32 [[XOR]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/GlobalISel/
Dlegalize-xor-scalar.mir47 ; CHECK: [[XOR:%[0-9]+]]:_(s8) = G_XOR [[TRUNC]], [[TRUNC1]]
72 ; CHECK: [[XOR:%[0-9]+]]:_(s8) = G_XOR [[DEF]], [[DEF]]
73 ; CHECK: $al = COPY [[XOR]](s8)
97 ; CHECK: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[DEF]], [[DEF]]
98 ; CHECK: $ax = COPY [[XOR]](s16)
122 ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[DEF]], [[DEF]]
123 ; CHECK: $eax = COPY [[XOR]](s32)
147 ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
148 ; CHECK: $rax = COPY [[XOR]](s64)
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/
DLanaiAluCode.h30 XOR = 0x06, enumerator
91 case XOR: in lanaiAluCodeToString()
112 .Case("xor", XOR) in stringToLanaiAluCode()
133 case ISD::XOR: in isdToLanaiAluCode()
134 return AluCode::XOR; in isdToLanaiAluCode()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dvec-xor-01.ll1 ; Test vector XOR.
5 ; Test a v16i8 XOR.
14 ; Test a v8i16 XOR.
23 ; Test a v4i32 XOR.
32 ; Test a v2i64 XOR.
Dvec-xor-02.ll1 ; Test vector NOT-XOR on z14.
5 ; Test a v16i8 NOT-XOR.
18 ; Test a v8i16 NOT-XOR.
29 ; Test a v4i32 NOT-XOR.
39 ; Test a v2i64 NOT-XOR.
Datomicrmw-xor-02.ll7 ; Check XOR of a variable.
48 ; Check the minimum signed value. We XOR the rotated word with 0x80000000.
77 ; Check XORs of -1. We XOR the rotated word with 0xffff0000.
91 ; Check XORs of 1. We XOR the rotated word with 0x00010000.
105 ; Check the maximum signed value. We XOR the rotated word with 0x7fff0000.
119 ; Check XORs of a large unsigned value. We XOR the rotated word with
Datomicrmw-xor-01.ll7 ; Check XOR of a variable.
48 ; Check the minimum signed value. We XOR the rotated word with 0x80000000.
77 ; Check XORs of -1. We XOR the rotated word with 0xff000000.
91 ; Check XORs of 1. We XOR the rotated word with 0x01000000.
105 ; Check the maximum signed value. We XOR the rotated word with 0x7f000000.
119 ; Check XORs of a large unsigned value. We XOR the rotated word with
/external/llvm/lib/Target/Lanai/
DLanaiAluCode.h30 XOR = 0x06, enumerator
91 case XOR: in lanaiAluCodeToString()
112 .Case("xor", XOR) in stringToLanaiAluCode()
133 case ISD::XOR: in isdToLanaiAluCode()
134 return AluCode::XOR; in isdToLanaiAluCode()
/external/llvm/test/CodeGen/SystemZ/
Dvec-xor-01.ll1 ; Test vector XOR.
5 ; Test a v16i8 XOR.
14 ; Test a v8i16 XOR.
23 ; Test a v4i32 XOR.
32 ; Test a v2i64 XOR.
Datomicrmw-xor-02.ll7 ; Check XOR of a variable.
48 ; Check the minimum signed value. We XOR the rotated word with 0x80000000.
77 ; Check XORs of -1. We XOR the rotated word with 0xffff0000.
91 ; Check XORs of 1. We XOR the rotated word with 0x00010000.
105 ; Check the maximum signed value. We XOR the rotated word with 0x7fff0000.
119 ; Check XORs of a large unsigned value. We XOR the rotated word with
Datomicrmw-xor-01.ll7 ; Check XOR of a variable.
48 ; Check the minimum signed value. We XOR the rotated word with 0x80000000.
77 ; Check XORs of -1. We XOR the rotated word with 0xff000000.
91 ; Check XORs of 1. We XOR the rotated word with 0x01000000.
105 ; Check the maximum signed value. We XOR the rotated word with 0x7f000000.
119 ; Check XORs of a large unsigned value. We XOR the rotated word with
/external/llvm/test/Transforms/InstCombine/
Dzext.ll39 ; CHECK-NEXT: [[XOR:%.*]] = and <2 x i64> [[TMP1]], <i64 23, i64 42>
40 ; CHECK-NEXT: ret <2 x i64> [[XOR]]
54 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[ZEXT1]], 1
55 ; CHECK-NEXT: [[ZEXT2:%.*]] = zext i32 [[XOR]] to i64
67 ; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i64> [[ZEXT1]], <i64 1, i64 1>
68 ; CHECK-NEXT: ret <2 x i64> [[XOR]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstSimplify/
DAndOrXor.ll611 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
612 ; CHECK-NEXT: ret i32 [[XOR]]
623 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
624 ; CHECK-NEXT: ret i32 [[XOR]]
638 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
639 ; CHECK-NEXT: ret i32 [[XOR]]
650 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[B:%.*]]
651 ; CHECK-NEXT: ret i32 [[XOR]]
665 ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[A:%.*]], [[NEGB]]
666 ; CHECK-NEXT: ret i32 [[XOR]]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dregbankselect-xor.mir15 ; CHECK: [[XOR:%[0-9]+]]:sgpr(s32) = G_XOR [[COPY]], [[COPY1]]
31 ; CHECK: [[XOR:%[0-9]+]]:vgpr(s32) = G_XOR [[COPY]], [[COPY1]]
48 ; CHECK: [[XOR:%[0-9]+]]:vgpr(s32) = G_XOR [[COPY]], [[COPY2]]
64 ; CHECK: [[XOR:%[0-9]+]]:vgpr(s32) = G_XOR [[COPY]], [[COPY1]]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsCondMov.td200 defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
209 defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>,
222 defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
224 defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
233 defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
234 defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
245 defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
247 defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
254 defm : MovzPats1<GPR32, FGR64, MOVZ_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
258 defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
/external/llvm/lib/Target/Mips/
DMipsCondMov.td201 defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
210 defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>,
223 defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
225 defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
234 defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
235 defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR>, INSN_MIPS4_32_NOT_32R6_64R6;
246 defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
248 defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
255 defm : MovzPats1<GPR32, FGR64, MOVZ_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
259 defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>, INSN_MIPS4_32_NOT_32R6_64R6,
/external/iptables/extensions/
Dlibxt_CONNMARK.man5 Zero out the bits given by \fImask\fP and XOR \fIvalue\fP into the ctmark.
14 nfmark to XOR into the ctmark. \fIctmask\fP and \fInfmask\fP default to
24 ctmark to XOR into the nfmark. \fIctmask\fP and \fInfmask\fP default to
40 Binary XOR the ctmark with \fIbits\fP. (Mnemonic for \fB\-\-set\-xmark\fP

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