| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 444 ZERO_EXTEND_VECTOR_INREG, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 489 ZERO_EXTEND_VECTOR_INREG, enumerator
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorOps.cpp | 330 case ISD::ZERO_EXTEND_VECTOR_INREG: in LegalizeOp()
685 case ISD::ZERO_EXTEND_VECTOR_INREG: in Expand()
|
| D | SelectionDAGDumper.cpp | 247 case ISD::ZERO_EXTEND_VECTOR_INREG: return "zero_extend_vector_inreg"; in getOperationName()
|
| D | LegalizeVectorTypes.cpp | 623 case ISD::ZERO_EXTEND_VECTOR_INREG: in SplitVectorResult()
2131 case ISD::ZERO_EXTEND_VECTOR_INREG: in WidenVectorResult()
2443 case ISD::ZERO_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
2461 case ISD::ZERO_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
|
| D | LegalizeIntegerTypes.cpp | 107 case ISD::ZERO_EXTEND_VECTOR_INREG: in PromoteIntegerResult()
3360 case ISD::ZERO_EXTEND_VECTOR_INREG: in PromoteIntRes_EXTEND_VECTOR_INREG()
|
| D | DAGCombiner.cpp | 1400 case ISD::ZERO_EXTEND_VECTOR_INREG: return visitZERO_EXTEND_VECTOR_INREG(N); in visit()
5788 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG) in tryToFoldExtendOfConstant()
|
| D | SelectionDAG.cpp | 1070 return getNode(ISD::ZERO_EXTEND_VECTOR_INREG, DL, VT, Op); in getZeroExtendVectorInReg()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 69 case ISD::ZERO_EXTEND_VECTOR_INREG: in ScalarizeVectorResult()
291 case ISD::ZERO_EXTEND_VECTOR_INREG: in ScalarizeVecRes_VecInregOp()
680 case ISD::ZERO_EXTEND_VECTOR_INREG: in SplitVectorResult()
1651 case ISD::ZERO_EXTEND_VECTOR_INREG: in SplitVectorOperand()
2339 case ISD::ZERO_EXTEND_VECTOR_INREG: in WidenVectorResult()
2660 case ISD::ZERO_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
2678 case ISD::ZERO_EXTEND_VECTOR_INREG: in WidenVecRes_EXTEND_VECTOR_INREG()
|
| D | LegalizeVectorOps.cpp | 389 case ISD::ZERO_EXTEND_VECTOR_INREG: in LegalizeOp()
715 case ISD::ZERO_EXTEND_VECTOR_INREG: in Expand()
|
| D | SelectionDAGDumper.cpp | 290 case ISD::ZERO_EXTEND_VECTOR_INREG: return "zero_extend_vector_inreg"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 109 case ISD::ZERO_EXTEND_VECTOR_INREG: in PromoteIntegerResult()
3516 case ISD::ZERO_EXTEND_VECTOR_INREG: in PromoteIntRes_EXTEND_VECTOR_INREG()
|
| D | SelectionDAG.cpp | 1151 return getNode(ISD::ZERO_EXTEND_VECTOR_INREG, DL, VT, Op); in getZeroExtendVectorInReg()
2682 case ISD::ZERO_EXTEND_VECTOR_INREG: { in computeKnownBits()
|
| D | DAGCombiner.cpp | 1555 case ISD::ZERO_EXTEND_VECTOR_INREG: return visitZERO_EXTEND_VECTOR_INREG(N); in visit()
7914 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG) in tryToFoldExtendOfConstant()
9249 N0.getOpcode() == ISD::ZERO_EXTEND_VECTOR_INREG) && in visitSIGN_EXTEND_INREG()
16755 Opcode != ISD::ZERO_EXTEND_VECTOR_INREG) in combineTruncationShuffle()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 86 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, T, Legal); in initializeHVXLowering()
141 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, T, Legal); in initializeHVXLowering()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 645 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
|
| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 900 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand); in initActions()
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 323 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom); in SystemZTargetLowering()
4579 case ISD::ZERO_EXTEND_VECTOR_INREG: in LowerOperation()
4779 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG || in combineExtract()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 388 def zext_invec : SDNode<"ISD::ZERO_EXTEND_VECTOR_INREG", SDTExtInvec>;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 348 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom); in SystemZTargetLowering()
4876 case ISD::ZERO_EXTEND_VECTOR_INREG: in LowerOperation()
5174 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG || in combineExtract()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 953 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Legal); in X86TargetLowering()
1323 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, MVT::v64i8, Custom); in X86TargetLowering()
1735 setTargetDAGCombine(ISD::ZERO_EXTEND_VECTOR_INREG); in X86TargetLowering()
6336 case ISD::ZERO_EXTEND_VECTOR_INREG: in getFauxShuffleMask()
19267 assert((Op.getOpcode() != ISD::ZERO_EXTEND_VECTOR_INREG || in LowerEXTEND_VECTOR_INREG()
22789 unsigned ExSSE41 = ISD::MULHU == Opcode ? ISD::ZERO_EXTEND_VECTOR_INREG in LowerMULH()
25317 case ISD::ZERO_EXTEND_VECTOR_INREG: in LowerOperation()
29177 Shuffle = unsigned(ISD::ZERO_EXTEND_VECTOR_INREG); in matchUnaryVectorShuffle()
33674 SDValue Res = DAG.getNode(Mode == MULU8 ? ISD::ZERO_EXTEND_VECTOR_INREG in reduceVMULWidth()
39285 (Opcode == X86ISD::VZEXT) || (Opcode == ISD::ZERO_EXTEND_VECTOR_INREG); in combineVSZext()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| D | X86GenFastISel.inc | 2230 // FastEmit functions for ISD::ZERO_EXTEND_VECTOR_INREG.
5522 …case ISD::ZERO_EXTEND_VECTOR_INREG: return fastEmit_ISD_ZERO_EXTEND_VECTOR_INREG_r(VT, RetVT, Op0,…
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 27570 SDValue Res = DAG.getNode(Mode == MULU8 ? ISD::ZERO_EXTEND_VECTOR_INREG in reduceVMULWidth()
|