| /external/clang/lib/StaticAnalyzer/Core/ |
| D | RegionStore.cpp | 1341 NonLoc ZeroIdx = svalBuilder.makeZeroArrayIndex(); in ArrayToPointer() local
1342 return loc::MemRegionVal(MRMgr.getElementRegion(T, ZeroIdx, R, Ctx)); in ArrayToPointer()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 5278 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl); in insert1BitVector() local
5292 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, Op, ZeroIdx); in insert1BitVector()
5308 ZeroIdx); in insert1BitVector()
5314 SubVec, ZeroIdx); in insert1BitVector()
5316 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, Op, ZeroIdx); in insert1BitVector()
5320 Undef, SubVec, ZeroIdx); in insert1BitVector()
5326 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx); in insert1BitVector()
5339 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OpVT, SubVec, ZeroIdx); in insert1BitVector()
5349 Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVecVT, Vec, ZeroIdx); in insert1BitVector()
5352 Vec, ZeroIdx); in insert1BitVector()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 3141 SDValue ZeroIdx = DAG.getConstant(0, SDLoc(Mask), IdxTy); in convertMask() local
3143 ZeroIdx); in convertMask()
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| D | LegalizeIntegerTypes.cpp | 729 SDValue ZeroIdx = DAG.getConstant(0, dl, IdxTy); in PromoteIntRes_TRUNCATE() local
730 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, WideExt, ZeroIdx); in PromoteIntRes_TRUNCATE()
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| D | DAGCombiner.cpp | 15556 SDValue ZeroIdx = DAG.getConstant(0, DL, IdxTy); in createBuildVecShuffle() local
15596 VecIn1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, VecIn1, ZeroIdx); in createBuildVecShuffle()
15616 DAG.getUNDEF(InVT1), VecIn2, ZeroIdx); in createBuildVecShuffle()
15667 Shuffle = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Shuffle, ZeroIdx); in createBuildVecShuffle()
17300 SDValue ZeroIdx = DAG.getConstant(0, SDLoc(N), IdxTy); in visitSCALAR_TO_VECTOR() local
17305 ZeroIdx); in visitSCALAR_TO_VECTOR()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 4591 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl); in insert1BitVector() local
4594 Undef, SubVec, ZeroIdx); in insert1BitVector()
4599 OpVT, V, ZeroIdx); in insert1BitVector()
4624 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, Undef, Vec, ZeroIdx); in insert1BitVector()
4630 SubVec, ZeroIdx); in insert1BitVector()
4641 Vec = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, WideOpVT, Undef, Vec, ZeroIdx); in insert1BitVector()
4649 SubVec, ZeroIdx); in insert1BitVector()
6986 SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl); in LowerCONCAT_VECTORSvXi1() local
6988 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx); in LowerCONCAT_VECTORSvXi1()
6990 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V1, ZeroIdx); in LowerCONCAT_VECTORSvXi1()
[all …]
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