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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2008-2011
4  * Graeme Russ, <graeme.russ@gmail.com>
5  *
6  * (C) Copyright 2002
7  * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
8  *
9  * Portions of this file are derived from the Linux kernel source
10  *  Copyright (C) 1991, 1992  Linus Torvalds
11  */
12 
13 #include <common.h>
14 #include <dm.h>
15 #include <asm/control_regs.h>
16 #include <asm/i8259.h>
17 #include <asm/interrupt.h>
18 #include <asm/io.h>
19 #include <asm/lapic.h>
20 #include <asm/processor-flags.h>
21 
22 DECLARE_GLOBAL_DATA_PTR;
23 
24 #define DECLARE_INTERRUPT(x) \
25 	".globl irq_"#x"\n" \
26 	".hidden irq_"#x"\n" \
27 	".type irq_"#x", @function\n" \
28 	"irq_"#x":\n" \
29 	"pushl $"#x"\n" \
30 	"jmp.d32 irq_common_entry\n"
31 
32 static char *exceptions[] = {
33 	"Divide Error",
34 	"Debug",
35 	"NMI Interrupt",
36 	"Breakpoint",
37 	"Overflow",
38 	"BOUND Range Exceeded",
39 	"Invalid Opcode (Undefined Opcode)",
40 	"Device Not Avaiable (No Math Coprocessor)",
41 	"Double Fault",
42 	"Coprocessor Segment Overrun",
43 	"Invalid TSS",
44 	"Segment Not Present",
45 	"Stack Segment Fault",
46 	"General Protection",
47 	"Page Fault",
48 	"Reserved",
49 	"x87 FPU Floating-Point Error",
50 	"Alignment Check",
51 	"Machine Check",
52 	"SIMD Floating-Point Exception",
53 	"Virtualization Exception",
54 	"Reserved",
55 	"Reserved",
56 	"Reserved",
57 	"Reserved",
58 	"Reserved",
59 	"Reserved",
60 	"Reserved",
61 	"Reserved",
62 	"Reserved",
63 	"Reserved",
64 	"Reserved"
65 };
66 
dump_regs(struct irq_regs * regs)67 static void dump_regs(struct irq_regs *regs)
68 {
69 	unsigned long cs, eip, eflags;
70 	unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
71 	unsigned long d0, d1, d2, d3, d6, d7;
72 	unsigned long sp;
73 
74 	/*
75 	 * Some exceptions cause an error code to be saved on the current stack
76 	 * after the EIP value. We should extract CS/EIP/EFLAGS from different
77 	 * position on the stack based on the exception number.
78 	 */
79 	switch (regs->irq_id) {
80 	case EXC_DF:
81 	case EXC_TS:
82 	case EXC_NP:
83 	case EXC_SS:
84 	case EXC_GP:
85 	case EXC_PF:
86 	case EXC_AC:
87 		cs = regs->context.ctx2.xcs;
88 		eip = regs->context.ctx2.eip;
89 		eflags = regs->context.ctx2.eflags;
90 		/* We should fix up the ESP due to error code */
91 		regs->esp += 4;
92 		break;
93 	default:
94 		cs = regs->context.ctx1.xcs;
95 		eip = regs->context.ctx1.eip;
96 		eflags = regs->context.ctx1.eflags;
97 		break;
98 	}
99 
100 	printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
101 			(u16)cs, eip, eflags);
102 	if (gd->flags & GD_FLG_RELOC)
103 		printf("Original EIP :[<%08lx>]\n", eip - gd->reloc_off);
104 
105 	printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
106 		regs->eax, regs->ebx, regs->ecx, regs->edx);
107 	printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
108 		regs->esi, regs->edi, regs->ebp, regs->esp);
109 	printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
110 	       (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs,
111 	       (u16)regs->xgs, (u16)regs->xss);
112 
113 	cr0 = read_cr0();
114 	cr2 = read_cr2();
115 	cr3 = read_cr3();
116 	cr4 = read_cr4();
117 
118 	printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
119 			cr0, cr2, cr3, cr4);
120 
121 	d0 = get_debugreg(0);
122 	d1 = get_debugreg(1);
123 	d2 = get_debugreg(2);
124 	d3 = get_debugreg(3);
125 
126 	printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
127 			d0, d1, d2, d3);
128 
129 	d6 = get_debugreg(6);
130 	d7 = get_debugreg(7);
131 	printf("DR6: %08lx DR7: %08lx\n",
132 			d6, d7);
133 
134 	printf("Stack:\n");
135 	sp = regs->esp;
136 
137 	sp += 64;
138 
139 	while (sp > (regs->esp - 16)) {
140 		if (sp == regs->esp)
141 			printf("--->");
142 		else
143 			printf("    ");
144 		printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
145 		sp -= 4;
146 	}
147 }
148 
do_exception(struct irq_regs * regs)149 static void do_exception(struct irq_regs *regs)
150 {
151 	printf("%s\n", exceptions[regs->irq_id]);
152 	dump_regs(regs);
153 	hang();
154 }
155 
156 struct idt_entry {
157 	u16	base_low;
158 	u16	selector;
159 	u8	res;
160 	u8	access;
161 	u16	base_high;
162 } __packed;
163 
164 struct desc_ptr {
165 	unsigned short size;
166 	unsigned long address;
167 } __packed;
168 
169 struct idt_entry idt[256] __aligned(16);
170 
171 struct desc_ptr idt_ptr;
172 
load_idt(const struct desc_ptr * dtr)173 static inline void load_idt(const struct desc_ptr *dtr)
174 {
175 	asm volatile("cs lidt %0" : : "m" (*dtr));
176 }
177 
set_vector(u8 intnum,void * routine)178 void set_vector(u8 intnum, void *routine)
179 {
180 	idt[intnum].base_high = (u16)((ulong)(routine) >> 16);
181 	idt[intnum].base_low = (u16)((ulong)(routine) & 0xffff);
182 }
183 
184 /*
185  * Ideally these would be defined static to avoid a checkpatch warning, but
186  * the compiler cannot see them in the inline asm and complains that they
187  * aren't defined
188  */
189 void irq_0(void);
190 void irq_1(void);
191 
cpu_init_interrupts(void)192 int cpu_init_interrupts(void)
193 {
194 	int i;
195 
196 	int irq_entry_size = irq_1 - irq_0;
197 	void *irq_entry = (void *)irq_0;
198 
199 	/* Setup the IDT */
200 	for (i = 0; i < 256; i++) {
201 		idt[i].access = 0x8e;
202 		idt[i].res = 0;
203 		idt[i].selector = X86_GDT_ENTRY_32BIT_CS * X86_GDT_ENTRY_SIZE;
204 		set_vector(i, irq_entry);
205 		irq_entry += irq_entry_size;
206 	}
207 
208 	idt_ptr.size = 256 * 8 - 1;
209 	idt_ptr.address = (unsigned long) idt;
210 
211 	load_idt(&idt_ptr);
212 
213 	return 0;
214 }
215 
x86_get_idt(void)216 void *x86_get_idt(void)
217 {
218 	return &idt_ptr;
219 }
220 
__do_irq(int irq)221 void __do_irq(int irq)
222 {
223 	printf("Unhandled IRQ : %d\n", irq);
224 }
225 void do_irq(int irq) __attribute__((weak, alias("__do_irq")));
226 
enable_interrupts(void)227 void enable_interrupts(void)
228 {
229 	asm("sti\n");
230 }
231 
disable_interrupts(void)232 int disable_interrupts(void)
233 {
234 	long flags;
235 
236 #if CONFIG_IS_ENABLED(X86_64)
237 	asm volatile ("pushfq ; popq %0 ; cli\n" : "=g" (flags) : );
238 #else
239 	asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
240 #endif
241 	return flags & X86_EFLAGS_IF;
242 }
243 
interrupt_init(void)244 int interrupt_init(void)
245 {
246 	struct udevice *dev;
247 	int ret;
248 
249 	/* Try to set up the interrupt router, but don't require one */
250 	ret = uclass_first_device_err(UCLASS_IRQ, &dev);
251 	if (ret && ret != -ENODEV)
252 		return ret;
253 
254 	/*
255 	 * When running as an EFI application we are not in control of
256 	 * interrupts and should leave them alone.
257 	 */
258 #ifndef CONFIG_EFI_APP
259 	/* Just in case... */
260 	disable_interrupts();
261 
262 #ifdef CONFIG_I8259_PIC
263 	/* Initialize the master/slave i8259 pic */
264 	i8259_init();
265 #endif
266 
267 	lapic_setup();
268 
269 	/* Initialize core interrupt and exception functionality of CPU */
270 	cpu_init_interrupts();
271 
272 	/*
273 	 * It is now safe to enable interrupts.
274 	 *
275 	 * TODO(sjg@chromium.org): But we don't handle these correctly when
276 	 * booted from EFI.
277 	 */
278 	if (ll_boot_init())
279 		enable_interrupts();
280 #endif
281 
282 	return 0;
283 }
284 
285 /* IRQ Low-Level Service Routine */
irq_llsr(struct irq_regs * regs)286 void irq_llsr(struct irq_regs *regs)
287 {
288 	/*
289 	 * For detailed description of each exception, refer to:
290 	 * Intel® 64 and IA-32 Architectures Software Developer's Manual
291 	 * Volume 1: Basic Architecture
292 	 * Order Number: 253665-029US, November 2008
293 	 * Table 6-1. Exceptions and Interrupts
294 	 */
295 	if (regs->irq_id < 32) {
296 		/* Architecture defined exception */
297 		do_exception(regs);
298 	} else {
299 		/* Hardware or User IRQ */
300 		do_irq(regs->irq_id);
301 	}
302 }
303 
304 /*
305  * OK - This looks really horrible, but it serves a purpose - It helps create
306  * fully relocatable code.
307  *  - The call to irq_llsr will be a relative jump
308  *  - The IRQ entries will be guaranteed to be in order
309  *  Interrupt entries are now very small (a push and a jump) but they are
310  *  now slower (all registers pushed on stack which provides complete
311  *  crash dumps in the low level handlers
312  *
313  * Interrupt Entry Point:
314  *  - Interrupt has caused eflags, CS and EIP to be pushed
315  *  - Interrupt Vector Handler has pushed orig_eax
316  *  - pt_regs.esp needs to be adjusted by 40 bytes:
317  *      12 bytes pushed by CPU (EFLAGSF, CS, EIP)
318  *      4 bytes pushed by vector handler (irq_id)
319  *      24 bytes pushed before SP (SS, GS, FS, ES, DS, EAX)
320  *      NOTE: Only longs are pushed on/popped off the stack!
321  */
322 asm(".globl irq_common_entry\n" \
323 	".hidden irq_common_entry\n" \
324 	".type irq_common_entry, @function\n" \
325 	"irq_common_entry:\n" \
326 	"cld\n" \
327 	"pushl %ss\n" \
328 	"pushl %gs\n" \
329 	"pushl %fs\n" \
330 	"pushl %es\n" \
331 	"pushl %ds\n" \
332 	"pushl %eax\n" \
333 	"movl  %esp, %eax\n" \
334 	"addl  $40, %eax\n" \
335 	"pushl %eax\n" \
336 	"pushl %ebp\n" \
337 	"pushl %edi\n" \
338 	"pushl %esi\n" \
339 	"pushl %edx\n" \
340 	"pushl %ecx\n" \
341 	"pushl %ebx\n" \
342 	"mov   %esp, %eax\n" \
343 	"call irq_llsr\n" \
344 	"popl %ebx\n" \
345 	"popl %ecx\n" \
346 	"popl %edx\n" \
347 	"popl %esi\n" \
348 	"popl %edi\n" \
349 	"popl %ebp\n" \
350 	"popl %eax\n" \
351 	"popl %eax\n" \
352 	"popl %ds\n" \
353 	"popl %es\n" \
354 	"popl %fs\n" \
355 	"popl %gs\n" \
356 	"popl %ss\n" \
357 	"add  $4, %esp\n" \
358 	"iret\n" \
359 	DECLARE_INTERRUPT(0) \
360 	DECLARE_INTERRUPT(1) \
361 	DECLARE_INTERRUPT(2) \
362 	DECLARE_INTERRUPT(3) \
363 	DECLARE_INTERRUPT(4) \
364 	DECLARE_INTERRUPT(5) \
365 	DECLARE_INTERRUPT(6) \
366 	DECLARE_INTERRUPT(7) \
367 	DECLARE_INTERRUPT(8) \
368 	DECLARE_INTERRUPT(9) \
369 	DECLARE_INTERRUPT(10) \
370 	DECLARE_INTERRUPT(11) \
371 	DECLARE_INTERRUPT(12) \
372 	DECLARE_INTERRUPT(13) \
373 	DECLARE_INTERRUPT(14) \
374 	DECLARE_INTERRUPT(15) \
375 	DECLARE_INTERRUPT(16) \
376 	DECLARE_INTERRUPT(17) \
377 	DECLARE_INTERRUPT(18) \
378 	DECLARE_INTERRUPT(19) \
379 	DECLARE_INTERRUPT(20) \
380 	DECLARE_INTERRUPT(21) \
381 	DECLARE_INTERRUPT(22) \
382 	DECLARE_INTERRUPT(23) \
383 	DECLARE_INTERRUPT(24) \
384 	DECLARE_INTERRUPT(25) \
385 	DECLARE_INTERRUPT(26) \
386 	DECLARE_INTERRUPT(27) \
387 	DECLARE_INTERRUPT(28) \
388 	DECLARE_INTERRUPT(29) \
389 	DECLARE_INTERRUPT(30) \
390 	DECLARE_INTERRUPT(31) \
391 	DECLARE_INTERRUPT(32) \
392 	DECLARE_INTERRUPT(33) \
393 	DECLARE_INTERRUPT(34) \
394 	DECLARE_INTERRUPT(35) \
395 	DECLARE_INTERRUPT(36) \
396 	DECLARE_INTERRUPT(37) \
397 	DECLARE_INTERRUPT(38) \
398 	DECLARE_INTERRUPT(39) \
399 	DECLARE_INTERRUPT(40) \
400 	DECLARE_INTERRUPT(41) \
401 	DECLARE_INTERRUPT(42) \
402 	DECLARE_INTERRUPT(43) \
403 	DECLARE_INTERRUPT(44) \
404 	DECLARE_INTERRUPT(45) \
405 	DECLARE_INTERRUPT(46) \
406 	DECLARE_INTERRUPT(47) \
407 	DECLARE_INTERRUPT(48) \
408 	DECLARE_INTERRUPT(49) \
409 	DECLARE_INTERRUPT(50) \
410 	DECLARE_INTERRUPT(51) \
411 	DECLARE_INTERRUPT(52) \
412 	DECLARE_INTERRUPT(53) \
413 	DECLARE_INTERRUPT(54) \
414 	DECLARE_INTERRUPT(55) \
415 	DECLARE_INTERRUPT(56) \
416 	DECLARE_INTERRUPT(57) \
417 	DECLARE_INTERRUPT(58) \
418 	DECLARE_INTERRUPT(59) \
419 	DECLARE_INTERRUPT(60) \
420 	DECLARE_INTERRUPT(61) \
421 	DECLARE_INTERRUPT(62) \
422 	DECLARE_INTERRUPT(63) \
423 	DECLARE_INTERRUPT(64) \
424 	DECLARE_INTERRUPT(65) \
425 	DECLARE_INTERRUPT(66) \
426 	DECLARE_INTERRUPT(67) \
427 	DECLARE_INTERRUPT(68) \
428 	DECLARE_INTERRUPT(69) \
429 	DECLARE_INTERRUPT(70) \
430 	DECLARE_INTERRUPT(71) \
431 	DECLARE_INTERRUPT(72) \
432 	DECLARE_INTERRUPT(73) \
433 	DECLARE_INTERRUPT(74) \
434 	DECLARE_INTERRUPT(75) \
435 	DECLARE_INTERRUPT(76) \
436 	DECLARE_INTERRUPT(77) \
437 	DECLARE_INTERRUPT(78) \
438 	DECLARE_INTERRUPT(79) \
439 	DECLARE_INTERRUPT(80) \
440 	DECLARE_INTERRUPT(81) \
441 	DECLARE_INTERRUPT(82) \
442 	DECLARE_INTERRUPT(83) \
443 	DECLARE_INTERRUPT(84) \
444 	DECLARE_INTERRUPT(85) \
445 	DECLARE_INTERRUPT(86) \
446 	DECLARE_INTERRUPT(87) \
447 	DECLARE_INTERRUPT(88) \
448 	DECLARE_INTERRUPT(89) \
449 	DECLARE_INTERRUPT(90) \
450 	DECLARE_INTERRUPT(91) \
451 	DECLARE_INTERRUPT(92) \
452 	DECLARE_INTERRUPT(93) \
453 	DECLARE_INTERRUPT(94) \
454 	DECLARE_INTERRUPT(95) \
455 	DECLARE_INTERRUPT(97) \
456 	DECLARE_INTERRUPT(96) \
457 	DECLARE_INTERRUPT(98) \
458 	DECLARE_INTERRUPT(99) \
459 	DECLARE_INTERRUPT(100) \
460 	DECLARE_INTERRUPT(101) \
461 	DECLARE_INTERRUPT(102) \
462 	DECLARE_INTERRUPT(103) \
463 	DECLARE_INTERRUPT(104) \
464 	DECLARE_INTERRUPT(105) \
465 	DECLARE_INTERRUPT(106) \
466 	DECLARE_INTERRUPT(107) \
467 	DECLARE_INTERRUPT(108) \
468 	DECLARE_INTERRUPT(109) \
469 	DECLARE_INTERRUPT(110) \
470 	DECLARE_INTERRUPT(111) \
471 	DECLARE_INTERRUPT(112) \
472 	DECLARE_INTERRUPT(113) \
473 	DECLARE_INTERRUPT(114) \
474 	DECLARE_INTERRUPT(115) \
475 	DECLARE_INTERRUPT(116) \
476 	DECLARE_INTERRUPT(117) \
477 	DECLARE_INTERRUPT(118) \
478 	DECLARE_INTERRUPT(119) \
479 	DECLARE_INTERRUPT(120) \
480 	DECLARE_INTERRUPT(121) \
481 	DECLARE_INTERRUPT(122) \
482 	DECLARE_INTERRUPT(123) \
483 	DECLARE_INTERRUPT(124) \
484 	DECLARE_INTERRUPT(125) \
485 	DECLARE_INTERRUPT(126) \
486 	DECLARE_INTERRUPT(127) \
487 	DECLARE_INTERRUPT(128) \
488 	DECLARE_INTERRUPT(129) \
489 	DECLARE_INTERRUPT(130) \
490 	DECLARE_INTERRUPT(131) \
491 	DECLARE_INTERRUPT(132) \
492 	DECLARE_INTERRUPT(133) \
493 	DECLARE_INTERRUPT(134) \
494 	DECLARE_INTERRUPT(135) \
495 	DECLARE_INTERRUPT(136) \
496 	DECLARE_INTERRUPT(137) \
497 	DECLARE_INTERRUPT(138) \
498 	DECLARE_INTERRUPT(139) \
499 	DECLARE_INTERRUPT(140) \
500 	DECLARE_INTERRUPT(141) \
501 	DECLARE_INTERRUPT(142) \
502 	DECLARE_INTERRUPT(143) \
503 	DECLARE_INTERRUPT(144) \
504 	DECLARE_INTERRUPT(145) \
505 	DECLARE_INTERRUPT(146) \
506 	DECLARE_INTERRUPT(147) \
507 	DECLARE_INTERRUPT(148) \
508 	DECLARE_INTERRUPT(149) \
509 	DECLARE_INTERRUPT(150) \
510 	DECLARE_INTERRUPT(151) \
511 	DECLARE_INTERRUPT(152) \
512 	DECLARE_INTERRUPT(153) \
513 	DECLARE_INTERRUPT(154) \
514 	DECLARE_INTERRUPT(155) \
515 	DECLARE_INTERRUPT(156) \
516 	DECLARE_INTERRUPT(157) \
517 	DECLARE_INTERRUPT(158) \
518 	DECLARE_INTERRUPT(159) \
519 	DECLARE_INTERRUPT(160) \
520 	DECLARE_INTERRUPT(161) \
521 	DECLARE_INTERRUPT(162) \
522 	DECLARE_INTERRUPT(163) \
523 	DECLARE_INTERRUPT(164) \
524 	DECLARE_INTERRUPT(165) \
525 	DECLARE_INTERRUPT(166) \
526 	DECLARE_INTERRUPT(167) \
527 	DECLARE_INTERRUPT(168) \
528 	DECLARE_INTERRUPT(169) \
529 	DECLARE_INTERRUPT(170) \
530 	DECLARE_INTERRUPT(171) \
531 	DECLARE_INTERRUPT(172) \
532 	DECLARE_INTERRUPT(173) \
533 	DECLARE_INTERRUPT(174) \
534 	DECLARE_INTERRUPT(175) \
535 	DECLARE_INTERRUPT(176) \
536 	DECLARE_INTERRUPT(177) \
537 	DECLARE_INTERRUPT(178) \
538 	DECLARE_INTERRUPT(179) \
539 	DECLARE_INTERRUPT(180) \
540 	DECLARE_INTERRUPT(181) \
541 	DECLARE_INTERRUPT(182) \
542 	DECLARE_INTERRUPT(183) \
543 	DECLARE_INTERRUPT(184) \
544 	DECLARE_INTERRUPT(185) \
545 	DECLARE_INTERRUPT(186) \
546 	DECLARE_INTERRUPT(187) \
547 	DECLARE_INTERRUPT(188) \
548 	DECLARE_INTERRUPT(189) \
549 	DECLARE_INTERRUPT(190) \
550 	DECLARE_INTERRUPT(191) \
551 	DECLARE_INTERRUPT(192) \
552 	DECLARE_INTERRUPT(193) \
553 	DECLARE_INTERRUPT(194) \
554 	DECLARE_INTERRUPT(195) \
555 	DECLARE_INTERRUPT(196) \
556 	DECLARE_INTERRUPT(197) \
557 	DECLARE_INTERRUPT(198) \
558 	DECLARE_INTERRUPT(199) \
559 	DECLARE_INTERRUPT(200) \
560 	DECLARE_INTERRUPT(201) \
561 	DECLARE_INTERRUPT(202) \
562 	DECLARE_INTERRUPT(203) \
563 	DECLARE_INTERRUPT(204) \
564 	DECLARE_INTERRUPT(205) \
565 	DECLARE_INTERRUPT(206) \
566 	DECLARE_INTERRUPT(207) \
567 	DECLARE_INTERRUPT(208) \
568 	DECLARE_INTERRUPT(209) \
569 	DECLARE_INTERRUPT(210) \
570 	DECLARE_INTERRUPT(211) \
571 	DECLARE_INTERRUPT(212) \
572 	DECLARE_INTERRUPT(213) \
573 	DECLARE_INTERRUPT(214) \
574 	DECLARE_INTERRUPT(215) \
575 	DECLARE_INTERRUPT(216) \
576 	DECLARE_INTERRUPT(217) \
577 	DECLARE_INTERRUPT(218) \
578 	DECLARE_INTERRUPT(219) \
579 	DECLARE_INTERRUPT(220) \
580 	DECLARE_INTERRUPT(221) \
581 	DECLARE_INTERRUPT(222) \
582 	DECLARE_INTERRUPT(223) \
583 	DECLARE_INTERRUPT(224) \
584 	DECLARE_INTERRUPT(225) \
585 	DECLARE_INTERRUPT(226) \
586 	DECLARE_INTERRUPT(227) \
587 	DECLARE_INTERRUPT(228) \
588 	DECLARE_INTERRUPT(229) \
589 	DECLARE_INTERRUPT(230) \
590 	DECLARE_INTERRUPT(231) \
591 	DECLARE_INTERRUPT(232) \
592 	DECLARE_INTERRUPT(233) \
593 	DECLARE_INTERRUPT(234) \
594 	DECLARE_INTERRUPT(235) \
595 	DECLARE_INTERRUPT(236) \
596 	DECLARE_INTERRUPT(237) \
597 	DECLARE_INTERRUPT(238) \
598 	DECLARE_INTERRUPT(239) \
599 	DECLARE_INTERRUPT(240) \
600 	DECLARE_INTERRUPT(241) \
601 	DECLARE_INTERRUPT(242) \
602 	DECLARE_INTERRUPT(243) \
603 	DECLARE_INTERRUPT(244) \
604 	DECLARE_INTERRUPT(245) \
605 	DECLARE_INTERRUPT(246) \
606 	DECLARE_INTERRUPT(247) \
607 	DECLARE_INTERRUPT(248) \
608 	DECLARE_INTERRUPT(249) \
609 	DECLARE_INTERRUPT(250) \
610 	DECLARE_INTERRUPT(251) \
611 	DECLARE_INTERRUPT(252) \
612 	DECLARE_INTERRUPT(253) \
613 	DECLARE_INTERRUPT(254) \
614 	DECLARE_INTERRUPT(255));
615