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Searched refs:aarch64 (Results 1 – 25 of 1804) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
D	loh.mir	1 # RUN: llc -o /dev/null %s -mtriple=aarch64-apple-ios -run-pass=aarch64-collect-loh -debug-only=aar… 25 ; CHECK-NEXT: $x1 = ADRP target-flags(aarch64-page) @g3 26 ; CHECK-NEXT: $x1 = ADRP target-flags(aarch64-page) @g4 28 ; CHECK-NEXT: $x1 = ADRP target-flags(aarch64-page) @g2 29 ; CHECK-NEXT: $x1 = ADRP target-flags(aarch64-page) @g3 31 ; CHECK-NEXT: $x0 = ADRP target-flags(aarch64-page) @g0 32 ; CHECK-NEXT: $x0 = ADRP target-flags(aarch64-page) @g1 33 $x0 = ADRP target-flags(aarch64-page) @g0 34 $x0 = ADRP target-flags(aarch64-page) @g1 35 $x1 = ADRP target-flags(aarch64-page) @g2 [all …]
D	misched-fusion-aes.ll	1 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mattr=+fuse-aes,+crypto \| FileCheck %s 2 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=generic -mattr=+crypto \| FileCheck %s 3 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a53 \| FileCheck %s 4 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a57 \| FileCheck %s 5 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a72 \| FileCheck %s 6 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=cortex-a73 \| FileCheck %s 7 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m1 \| FileCheck %s 8 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m2 \| FileCheck %s 9 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m3 \| FileCheck %s 10 ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m4 \| FileCheck %s [all …]
D	arm64-cvt.ll	1 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple \| FileCheck %s 10 %tmp3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f32(float %A) 18 %tmp3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f32(float %A) 26 %tmp3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f64(double %A) 34 %tmp3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f64(double %A) 38 declare i32 @llvm.aarch64.neon.fcvtas.i32.f32(float) nounwind readnone 39 declare i64 @llvm.aarch64.neon.fcvtas.i64.f32(float) nounwind readnone 40 declare i32 @llvm.aarch64.neon.fcvtas.i32.f64(double) nounwind readnone 41 declare i64 @llvm.aarch64.neon.fcvtas.i64.f64(double) nounwind readnone 50 %tmp3 = call i32 @llvm.aarch64.neon.fcvtau.i32.f32(float %A) [all …]
D	arm64-neon-across.ll	3 declare float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float>) 5 declare float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float>) 7 declare float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float>) 9 declare float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float>) 11 declare i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32>) 13 declare i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16>) 15 declare i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8>) 17 declare i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16>) 19 declare i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8>) 21 declare i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32>) [all …]
D	arm64-vsqrt.ll	1 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple \| FileCheck %s 8 %tmp3 = call <2 x float> @llvm.aarch64.neon.frecps.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) 17 %tmp3 = call <4 x float> @llvm.aarch64.neon.frecps.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) 26 %tmp3 = call <2 x double> @llvm.aarch64.neon.frecps.v2f64(<2 x double> %tmp1, <2 x double> %tmp2) 30 declare <2 x float> @llvm.aarch64.neon.frecps.v2f32(<2 x float>, <2 x float>) nounwind readnone 31 declare <4 x float> @llvm.aarch64.neon.frecps.v4f32(<4 x float>, <4 x float>) nounwind readnone 32 declare <2 x double> @llvm.aarch64.neon.frecps.v2f64(<2 x double>, <2 x double>) nounwind readnone 40 %tmp3 = call <2 x float> @llvm.aarch64.neon.frsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) 49 %tmp3 = call <4 x float> @llvm.aarch64.neon.frsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) 58 %tmp3 = call <2 x double> @llvm.aarch64.neon.frsqrts.v2f64(<2 x double> %tmp1, <2 x double> %tmp2) [all …]
D	arm64-fminv.ll	6 %min = call float @llvm.aarch64.neon.fminv.f32.v2f32(<2 x float> %in) 13 %min = call float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float> %in) 20 %min = call double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double> %in) 24 declare float @llvm.aarch64.neon.fminv.f32.v2f32(<2 x float>) 25 declare float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float>) 26 declare double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double>) 31 %max = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> %in) 38 %max = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> %in) 45 %max = call double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double> %in) 49 declare float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float>) [all …]
D	arm64-ldxr-stxr.ll	9 %ldrexd = tail call %0 @llvm.aarch64.ldxp(i8* %p) 26 %strexd = tail call i32 @llvm.aarch64.stxp(i64 %tmp4, i64 %tmp7, i8* %ptr) 30 declare %0 @llvm.aarch64.ldxp(i8) nounwind 31 declare i32 @llvm.aarch64.stxp(i64, i64, i8) nounwind 42 %val = call i64 @llvm.aarch64.ldxr.p0i8(i8* %addr) 56 %val = call i64 @llvm.aarch64.ldxr.p0i16(i16* %addr) 70 %val = call i64 @llvm.aarch64.ldxr.p0i32(i32* %addr) 82 %val = call i64 @llvm.aarch64.ldxr.p0i64(i64* %addr) 88 declare i64 @llvm.aarch64.ldxr.p0i8(i8) nounwind 89 declare i64 @llvm.aarch64.ldxr.p0i16(i16) nounwind [all …]
D	arm64-vqadd.ll	1 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple \| FileCheck %s 8 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) 17 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) 26 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) 35 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) 44 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) 53 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) 62 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) 71 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) 80 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) [all …]
D	arm64-vmax.ll	1 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple \| FileCheck %s 8 %tmp3 = call <8 x i8> @llvm.aarch64.neon.smax.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) 17 %tmp3 = call <16 x i8> @llvm.aarch64.neon.smax.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) 26 %tmp3 = call <4 x i16> @llvm.aarch64.neon.smax.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) 35 %tmp3 = call <8 x i16> @llvm.aarch64.neon.smax.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) 44 %tmp3 = call <2 x i32> @llvm.aarch64.neon.smax.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) 53 %tmp3 = call <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) 57 declare <8 x i8> @llvm.aarch64.neon.smax.v8i8(<8 x i8>, <8 x i8>) nounwind readnone 58 declare <16 x i8> @llvm.aarch64.neon.smax.v16i8(<16 x i8>, <16 x i8>) nounwind readnone 59 declare <4 x i16> @llvm.aarch64.neon.smax.v4i16(<4 x i16>, <4 x i16>) nounwind readnone [all …]
D	preferred-function-alignment.ll	1 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=generic < %s \| FileCheck --check-prefixes=ALIGN2,CH… 2 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a35 < %s \| FileCheck --check-prefixes=ALIGN2… 3 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cyclone < %s \| FileCheck --check-prefixes=ALIGN2,CH… 4 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=falkor < %s \| FileCheck --check-prefixes=ALIGN2,CHE… 5 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=kryo < %s \| FileCheck --check-prefixes=ALIGN2,CHECK… 6 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=cortex-a53 < %s \| FileCheck --check-prefixes=ALIGN3… 7 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderx < %s \| FileCheck --check-prefixes=ALIGN3,C… 8 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt81 < %s \| FileCheck --check-prefixes=ALIGN… 9 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt83 < %s \| FileCheck --check-prefixes=ALIGN… 10 ; RUN: llc -mtriple=aarch64-unknown-linux -mcpu=thunderxt88 < %s \| FileCheck --check-prefixes=ALIGN… [all …]
D	remat.ll	1 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a35 -o - %s \| FileCheck %s 2 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a53 -o - %s \| FileCheck %s 3 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a55 -o - %s \| FileCheck %s 4 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a57 -o - %s \| FileCheck %s 5 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a72 -o - %s \| FileCheck %s 6 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a73 -o - %s \| FileCheck %s 7 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a75 -o - %s \| FileCheck %s 8 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m1 -o - %s \| FileCheck %s 9 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m2 -o - %s \| FileCheck %s 10 ; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m3 -o - %s \| FileCheck %s [all …]
D	fp16_intrinsic_scalar_1op.ll	1 ; RUN: llc < %s -mtriple=aarch64-eabi -mattr=+v8.2a,+fullfp16 \| FileCheck %s 3 declare i64 @llvm.aarch64.neon.fcvtpu.i64.f16(half) 4 declare i32 @llvm.aarch64.neon.fcvtpu.i32.f16(half) 5 declare i64 @llvm.aarch64.neon.fcvtps.i64.f16(half) 6 declare i32 @llvm.aarch64.neon.fcvtps.i32.f16(half) 7 declare i64 @llvm.aarch64.neon.fcvtnu.i64.f16(half) 8 declare i32 @llvm.aarch64.neon.fcvtnu.i32.f16(half) 9 declare i64 @llvm.aarch64.neon.fcvtns.i64.f16(half) 10 declare i32 @llvm.aarch64.neon.fcvtns.i32.f16(half) 11 declare i64 @llvm.aarch64.neon.fcvtmu.i64.f16(half) [all …]
D	arm64-crypto.ll	1 ; RUN: llc -mtriple=arm64-eabi -mattr=crypto -aarch64-neon-syntax=apple -o - %s \| FileCheck %s 3 declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %data, <16 x i8> %key) 4 declare <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> %data, <16 x i8> %key) 5 declare <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %data) 6 declare <16 x i8> @llvm.aarch64.crypto.aesimc(<16 x i8> %data) 11 %res = call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %data, <16 x i8> %key) 18 %res = call <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> %data, <16 x i8> %key) 25 %res = call <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %data) 32 %res = call <16 x i8> @llvm.aarch64.crypto.aesimc(<16 x i8> %data) 36 declare <4 x i32> @llvm.aarch64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) [all …]
/external/vixl/test/
D	test-code-generation-scopes.cc	69 aarch64::MacroAssembler masm; in TEST() 72 CodeBufferCheckScope scope(&masm, aarch64::kInstructionSize); in TEST() 73 __ Mov(aarch64::x0, 0); in TEST() 98 aarch64::MacroAssembler masm; in TEST() 101 CodeBufferCheckScope scope(&masm, 2 * aarch64::kInstructionSize); in TEST() 102 __ Mov(aarch64::x0, 0); in TEST() 103 __ movz(aarch64::x1, 1); in TEST() 129 aarch64::MacroAssembler masm; in TEST() 133 __ Mov(aarch64::x0, 0); in TEST() 134 scope.Open(&masm, aarch64::kInstructionSize); in TEST() [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/MIR/AArch64/
D	target-flags.mir	1 # RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s \| FileCheck %s 24 ; CHECK: $x8 = ADRP target-flags(aarch64-page) @var_i32 25 ; CHECK-NEXT: $x9 = ADRP target-flags(aarch64-page) @var_i64 26 ; CHECK-NEXT: $w10 = LDRWui $x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32 27 ; CHECK-NEXT: $x11 = LDRXui $x9, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @var_i64 28 ; CHECK: STRWui killed $w10, killed $x8, target-flags(aarch64-nc) @var_i32 29 ; CHECK: STRXui killed $x11, killed $x9, target-flags(aarch64-pageoff, aarch64-nc) @var_i64 30 $x8 = ADRP target-flags(aarch64-page) @var_i32 31 $x9 = ADRP target-flags(aarch64-page) @var_i64 32 $w10 = LDRWui $x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32 [all …]
/external/llvm/test/CodeGen/MIR/AArch64/
D	target-flags.mir	1 # RUN: llc -mtriple=aarch64-none-linux-gnu -start-after branch-folder -stop-after branch-folder -o … 24 ; CHECK: %x8 = ADRP target-flags(aarch64-page) @var_i32 25 ; CHECK-NEXT: %x9 = ADRP target-flags(aarch64-page) @var_i64 26 ; CHECK-NEXT: %w10 = LDRWui %x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32 27 ; CHECK-NEXT: %x11 = LDRXui %x9, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @var_i64 28 ; CHECK: STRWui killed %w10, killed %x8, target-flags(aarch64-nc) @var_i32 29 ; CHECK: STRXui killed %x11, killed %x9, target-flags(aarch64-pageoff, aarch64-nc) @var_i64 30 %x8 = ADRP target-flags(aarch64-page) @var_i32 31 %x9 = ADRP target-flags(aarch64-page) @var_i64 32 %w10 = LDRWui %x8, target-flags(aarch64-pageoff, aarch64-nc) @var_i32 [all …]
/external/llvm/test/CodeGen/AArch64/
D	arm64-cvt.ll	1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple \| FileCheck %s 10 %tmp3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f32(float %A) 18 %tmp3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f32(float %A) 26 %tmp3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f64(double %A) 34 %tmp3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f64(double %A) 38 declare i32 @llvm.aarch64.neon.fcvtas.i32.f32(float) nounwind readnone 39 declare i64 @llvm.aarch64.neon.fcvtas.i64.f32(float) nounwind readnone 40 declare i32 @llvm.aarch64.neon.fcvtas.i32.f64(double) nounwind readnone 41 declare i64 @llvm.aarch64.neon.fcvtas.i64.f64(double) nounwind readnone 50 %tmp3 = call i32 @llvm.aarch64.neon.fcvtau.i32.f32(float %A) [all …]
D	arm64-neon-across.ll	3 declare float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float>) 5 declare float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float>) 7 declare float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float>) 9 declare float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float>) 11 declare i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32>) 13 declare i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16>) 15 declare i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8>) 17 declare i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16>) 19 declare i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8>) 21 declare i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32>) [all …]
D	arm64-vsqrt.ll	1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple \| FileCheck %s 8 %tmp3 = call <2 x float> @llvm.aarch64.neon.frecps.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) 17 %tmp3 = call <4 x float> @llvm.aarch64.neon.frecps.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) 26 %tmp3 = call <2 x double> @llvm.aarch64.neon.frecps.v2f64(<2 x double> %tmp1, <2 x double> %tmp2) 30 declare <2 x float> @llvm.aarch64.neon.frecps.v2f32(<2 x float>, <2 x float>) nounwind readnone 31 declare <4 x float> @llvm.aarch64.neon.frecps.v4f32(<4 x float>, <4 x float>) nounwind readnone 32 declare <2 x double> @llvm.aarch64.neon.frecps.v2f64(<2 x double>, <2 x double>) nounwind readnone 40 %tmp3 = call <2 x float> @llvm.aarch64.neon.frsqrts.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) 49 %tmp3 = call <4 x float> @llvm.aarch64.neon.frsqrts.v4f32(<4 x float> %tmp1, <4 x float> %tmp2) 58 %tmp3 = call <2 x double> @llvm.aarch64.neon.frsqrts.v2f64(<2 x double> %tmp1, <2 x double> %tmp2) [all …]
D	arm64-fminv.ll	6 %min = call float @llvm.aarch64.neon.fminv.f32.v2f32(<2 x float> %in) 13 %min = call float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float> %in) 20 %min = call double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double> %in) 24 declare float @llvm.aarch64.neon.fminv.f32.v2f32(<2 x float>) 25 declare float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float>) 26 declare double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double>) 31 %max = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> %in) 38 %max = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> %in) 45 %max = call double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double> %in) 49 declare float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float>) [all …]
D	arm64-ldxr-stxr.ll	9 %ldrexd = tail call %0 @llvm.aarch64.ldxp(i8* %p) 26 %strexd = tail call i32 @llvm.aarch64.stxp(i64 %tmp4, i64 %tmp7, i8* %ptr) 30 declare %0 @llvm.aarch64.ldxp(i8) nounwind 31 declare i32 @llvm.aarch64.stxp(i64, i64, i8) nounwind 42 %val = call i64 @llvm.aarch64.ldxr.p0i8(i8* %addr) 56 %val = call i64 @llvm.aarch64.ldxr.p0i16(i16* %addr) 70 %val = call i64 @llvm.aarch64.ldxr.p0i32(i32* %addr) 82 %val = call i64 @llvm.aarch64.ldxr.p0i64(i64* %addr) 88 declare i64 @llvm.aarch64.ldxr.p0i8(i8) nounwind 89 declare i64 @llvm.aarch64.ldxr.p0i16(i16) nounwind [all …]
D	arm64-vqadd.ll	1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple \| FileCheck %s 8 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) 17 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) 26 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) 35 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) 44 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) 53 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) 62 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) 71 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) 80 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) [all …]
D	arm64-vmax.ll	1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple \| FileCheck %s 8 %tmp3 = call <8 x i8> @llvm.aarch64.neon.smax.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) 17 %tmp3 = call <16 x i8> @llvm.aarch64.neon.smax.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2) 26 %tmp3 = call <4 x i16> @llvm.aarch64.neon.smax.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) 35 %tmp3 = call <8 x i16> @llvm.aarch64.neon.smax.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2) 44 %tmp3 = call <2 x i32> @llvm.aarch64.neon.smax.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) 53 %tmp3 = call <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2) 57 declare <8 x i8> @llvm.aarch64.neon.smax.v8i8(<8 x i8>, <8 x i8>) nounwind readnone 58 declare <16 x i8> @llvm.aarch64.neon.smax.v16i8(<16 x i8>, <16 x i8>) nounwind readnone 59 declare <4 x i16> @llvm.aarch64.neon.smax.v4i16(<4 x i16>, <4 x i16>) nounwind readnone [all …]
D	arm64-crypto.ll	1 ; RUN: llc -march=arm64 -mattr=crypto -aarch64-neon-syntax=apple -o - %s \| FileCheck %s 3 declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %data, <16 x i8> %key) 4 declare <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> %data, <16 x i8> %key) 5 declare <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %data) 6 declare <16 x i8> @llvm.aarch64.crypto.aesimc(<16 x i8> %data) 11 %res = call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %data, <16 x i8> %key) 18 %res = call <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> %data, <16 x i8> %key) 25 %res = call <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %data) 32 %res = call <16 x i8> @llvm.aarch64.crypto.aesimc(<16 x i8> %data) 36 declare <4 x i32> @llvm.aarch64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk) [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/GlobalISel/
D	select-blockaddress.mir	2 # RUN: llc -mtriple=aarch64-unknown-unknown -o - -verify-machineinstrs -run-pass=instruction-select… 3 # RUN: llc -mtriple=aarch64-unknown-unknown -o - -verify-machineinstrs -run-pass=instruction-select… 8 target triple = "aarch64-none-linux-gnu" 34 …= MOVaddrBA target-flags(aarch64-page) blockaddress(@test_blockaddress, %ir-block.block), target-f… 35 …r:%[0-9]+]]:gpr64common = MOVaddr target-flags(aarch64-page) @addr, target-flags(aarch64-pageoff, … 43 …; LARGE: [[MOVZXi:%[0-9]+]]:gpr64 = MOVZXi target-flags(aarch64-g0, aarch64-nc) blockaddress(@te… 44 …; LARGE: [[MOVKXi:%[0-9]+]]:gpr64 = MOVKXi [[MOVZXi]], target-flags(aarch64-g1, aarch64-nc) bloc… 45 …; LARGE: [[MOVKXi1:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi]], target-flags(aarch64-g2, aarch64-nc) blo… 46 …; LARGE: [[MOVKXi2:%[0-9]+]]:gpr64 = MOVKXi [[MOVKXi1]], target-flags(aarch64-g3) blockaddress(@… 47 ; LARGE: [[MOVZXi1:%[0-9]+]]:gpr64 = MOVZXi target-flags(aarch64-g0, aarch64-nc) @addr, 0 [all …]

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