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/external/skia/src/core/
DSkCpu.cpp14 static void cpuid (uint32_t abcd[4]) { __cpuid ((int*)abcd, 1); } in cpuid()
15 static void cpuid7(uint32_t abcd[4]) { __cpuidex((int*)abcd, 7, 0); } in cpuid7()
23 static void cpuid (uint32_t abcd[4]) { __get_cpuid(1, abcd+0, abcd+1, abcd+2, abcd+3); } in cpuid()
24 static void cpuid7(uint32_t abcd[4]) { in cpuid7()
25 __cpuid_count(7, 0, abcd[0], abcd[1], abcd[2], abcd[3]); in cpuid7()
36 uint32_t abcd[4] = {0,0,0,0}; in read_cpu_features() local
40 cpuid(abcd); in read_cpu_features()
41 if (abcd[3] & (1<<25)) { features |= SkCpu:: SSE1; } in read_cpu_features()
42 if (abcd[3] & (1<<26)) { features |= SkCpu:: SSE2; } in read_cpu_features()
43 if (abcd[2] & (1<< 0)) { features |= SkCpu:: SSE3; } in read_cpu_features()
[all …]
/external/skqp/src/core/
DSkCpu.cpp14 static void cpuid (uint32_t abcd[4]) { __cpuid ((int*)abcd, 1); } in cpuid()
15 static void cpuid7(uint32_t abcd[4]) { __cpuidex((int*)abcd, 7, 0); } in cpuid7()
23 static void cpuid (uint32_t abcd[4]) { __get_cpuid(1, abcd+0, abcd+1, abcd+2, abcd+3); } in cpuid()
24 static void cpuid7(uint32_t abcd[4]) { in cpuid7()
25 __cpuid_count(7, 0, abcd[0], abcd[1], abcd[2], abcd[3]); in cpuid7()
36 uint32_t abcd[4] = {0,0,0,0}; in read_cpu_features() local
40 cpuid(abcd); in read_cpu_features()
41 if (abcd[3] & (1<<25)) { features |= SkCpu:: SSE1; } in read_cpu_features()
42 if (abcd[3] & (1<<26)) { features |= SkCpu:: SSE2; } in read_cpu_features()
43 if (abcd[2] & (1<< 0)) { features |= SkCpu:: SSE3; } in read_cpu_features()
[all …]
/external/eigen/bench/
Dcheck_cache_queries.cpp10 int abcd[4]; \
11 abcd[0] = abcd[1] = abcd[2] = abcd[3] = 0;\
12 EIGEN_CPUID(abcd, CODE, 0); \
14 << (int*)(abcd[0]) << " " << (int*)(abcd[1]) << " " \
15 << (int*)(abcd[2]) << " " << (int*)(abcd[3]) << " " << std::endl; \
28 int abcd[4]; in main() local
33 EIGEN_CPUID(abcd,0x0,0); in main()
34 string[0] = abcd[1]; in main()
35 string[1] = abcd[3]; in main()
36 string[2] = abcd[2]; in main()
[all …]
/external/pcre/dist2/testdata/
Dtestoutput20101 /abcd/pushcopy
102 abcd
103 0: abcd
106 abcd
107 0: abcd
112 /abcd/push
114 abcd
115 0: abcd
118 abcd
119 0: abcd
[all …]
Dtestinput2063 /abcd/pushcopy
64 abcd
67 abcd
71 /abcd/push
73 abcd
76 abcd
78 /abcd/push
84 abcd
87 abcd
91 /abcd/pushtablescopy
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Dtestinput15129 abcd
132 abcd
136 abcd
140 abcd
148 abcd
153 abcd
156 abcd
159 abcd
166 abcd
/external/eigen/Eigen/src/Core/util/
DMemory.h757 # define EIGEN_CPUID(abcd,func,id) \
758 …("xchgl %%ebx, %k1;cpuid; xchgl %%ebx,%k1": "=a" (abcd[0]), "=&r" (abcd[1]), "=c" (abcd[2]), "=d" …
762 # define EIGEN_CPUID(abcd,func,id) \
763 …%%}rbx, %q1; cpuid; xchg{q}\t{%%}rbx, %q1": "=a" (abcd[0]), "=&r" (abcd[1]), "=c" (abcd[2]), "=d" …
766 # define EIGEN_CPUID(abcd,func,id) \
767 …__asm__ __volatile__ ("cpuid": "=a" (abcd[0]), "=b" (abcd[1]), "=c" (abcd[2]), "=d" (abcd[3]) : "0…
771 # define EIGEN_CPUID(abcd,func,id) __cpuidex((int*)abcd,func,id)
780 inline bool cpuid_is_vendor(int abcd[4], const int vendor[3])
782 return abcd[1]==vendor[0] && abcd[3]==vendor[1] && abcd[2]==vendor[2];
787 int abcd[4];
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/external/icu/icu4c/source/test/intltest/
Dstrtest.cpp209 StringPiece abcd(abcdefg_chars, 4); in TestStringPiece() local
210 if(abcd.empty() || abcd.data()!=abcdefg_chars || abcd.length()!=4 || abcd.size()!=4) { in TestStringPiece()
220 StringPiece sp(abcd, -1); in TestStringPiece()
224 sp=StringPiece(abcd, 5); in TestStringPiece()
228 sp=StringPiece(abcd, 2); in TestStringPiece()
233 sp=StringPiece(abcd, -1, 8); in TestStringPiece()
237 sp=StringPiece(abcd, 5, 8); in TestStringPiece()
241 sp=StringPiece(abcd, 2, 8); in TestStringPiece()
245 sp=StringPiece(abcd, 2, -1); in TestStringPiece()
255 sp=abcd.substr(-1); in TestStringPiece()
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/external/llvm/test/CodeGen/X86/
Dh-registers-1.ll10 ; CHECK: movzbl %{{[abcd]}}h, %e
11 ; CHECK: movzbl %{{[abcd]}}h, %e
12 ; CHECK: movzbl %{{[abcd]}}h, %e
13 ; CHECK: movzbl %{{[abcd]}}h, %e
14 ; CHECK: movzbl %{{[abcd]}}h, %e
15 ; CHECK: movzbl %{{[abcd]}}h, %e
16 ; CHECK: movzbl %{{[abcd]}}h, %e
17 ; CHECK: movzbl %{{[abcd]}}h, %e
Dh-register-addressing-32.ll13 ; CHECK: movzbl %{{[abcd]}}h, %e
23 ; CHECK: movzbl %{{[abcd]}}h, %e
33 ; CHECK: movzbl %{{[abcd]}}h, %e
43 ; CHECK: movzbl %{{[abcd]}}h, %e
53 ; CHECK: movzbl %{{[abcd]}}h, %e
63 ; CHECK: movzbl %{{[abcd]}}h, %e
73 ; CHECK: movzbl %{{[abcd]}}h, %e
Dh-register-addressing-64.ll13 ; CHECK: movzbl %{{[abcd]}}h, %e
23 ; CHECK: movzbl %{{[abcd]}}h, %e
33 ; CHECK: movzbl %{{[abcd]}}h, %e
43 ; CHECK: movzbl %{{[abcd]}}h, %e
53 ; CHECK: movzbl %{{[abcd]}}h, %e
63 ; CHECK: movzbl %{{[abcd]}}h, %e
73 ; CHECK: movzbl %{{[abcd]}}h, %e
/external/icu/icu4c/source/test/testdata/
Dre_tests.txt129 ab|cd abcd y $& ab
172 ([abc])*bcd abcd y $&-$1 abcd-a
179 abcd*efg abcdefg y $& abcdefg
186 (a|b)c*d abcd y $&-$1 bcd-b
189 a([bc]*)(c*d) abcd y $&-$1-$2 abcd-bc-d
190 a([bc]*)(c*d) abcd y $-[0] 0
191 a([bc]*)(c*d) abcd y $+[0] 4
192 a([bc]*)(c*d) abcd y $-[1] 1
193 a([bc]*)(c*d) abcd y $+[1] 3
194 a([bc]*)(c*d) abcd y $-[2] 3
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/X86/
Dblend_x86.ll26 define <4 x float> @constant_blendvps(<4 x float> %xyzw, <4 x float> %abcd) {
28 ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> %abcd, <4 x float> %xyzw, <4 x i32> <i32 …
31 …%1 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %xyzw, <4 x float> %abcd, <4 x flo…
35 define <4 x float> @constant_blendvps_zero(<4 x float> %xyzw, <4 x float> %abcd) {
38 …%1 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %xyzw, <4 x float> %abcd, <4 x flo…
49 define <16 x i8> @constant_pblendvb(<16 x i8> %xyzw, <16 x i8> %abcd) {
51 ; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i8> %abcd, <16 x i8> %xyzw, <16 x i32> <i32 16,…
54 …%1 = tail call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> %xyzw, <16 x i8> %abcd, <16 x i8> <i8 …
58 define <16 x i8> @constant_pblendvb_zero(<16 x i8> %xyzw, <16 x i8> %abcd) {
61 …%1 = tail call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> %xyzw, <16 x i8> %abcd, <16 x i8> zero…
[all …]
/external/llvm/test/Transforms/InstCombine/
Dblend_x86.ll25 define <4 x float> @constant_blendvps(<4 x float> %xyzw, <4 x float> %abcd) {
27 ; CHECK-NEXT: %1 = select <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x float> %abcd, <4 x…
29 …%1 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %xyzw, <4 x float> %abcd, <4 x flo…
33 define <4 x float> @constant_blendvps_zero(<4 x float> %xyzw, <4 x float> %abcd) {
36 …%1 = tail call <4 x float> @llvm.x86.sse41.blendvps(<4 x float> %xyzw, <4 x float> %abcd, <4 x flo…
47 define <16 x i8> @constant_pblendvb(<16 x i8> %xyzw, <16 x i8> %abcd) {
49 …i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false>, <16 x i8> %abcd, <16 x i8> %xyzw
51 …%1 = tail call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> %xyzw, <16 x i8> %abcd, <16 x i8> <i8 …
55 define <16 x i8> @constant_pblendvb_zero(<16 x i8> %xyzw, <16 x i8> %abcd) {
58 …%1 = tail call <16 x i8> @llvm.x86.sse41.pblendvb(<16 x i8> %xyzw, <16 x i8> %abcd, <16 x i8> zero…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/NVPTX/
Dwmma.py10 def make_wmma_slice_ty(abcd, itype): argument
12 num_elts = 4 if abcd in "cd" and itype == "f16" else 8;
108 def make_wmma_slice_args(itype, abcd, prefix="v"): argument
110 in enumerate(make_wmma_slice_ty(abcd, itype))])
219 args = ",\n ".join(make_wmma_slice_args(t, abcd, prefix=abcd)
220 for abcd, t in (("a", "f16"),
/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-strings/
Dfile-filename.test1 RUN: llvm-strings -f %S/Inputs/abcd | FileCheck %s
2 RUN: llvm-strings --print-file-name %S/Inputs/abcd | FileCheck %s
3 CHECK: {{[\\/]}}abcd: abcd
Dlength.test9 STDIN: abcd
11 CHECK-DEFAULT: abcd
18 CHECK-1: abcd
23 CHECK-2: abcd
/external/libcups/cups/
Dmd5.c116 a = pms->abcd[0], b = pms->abcd[1], in _cups_md5_process()
117 c = pms->abcd[2], d = pms->abcd[3]; in _cups_md5_process()
265 pms->abcd[0] += a; in _cups_md5_process()
266 pms->abcd[1] += b; in _cups_md5_process()
267 pms->abcd[2] += c; in _cups_md5_process()
268 pms->abcd[3] += d; in _cups_md5_process()
275 pms->abcd[0] = 0x67452301; in _cupsMD5Init()
276 pms->abcd[1] = 0xefcdab89; in _cupsMD5Init()
277 pms->abcd[2] = 0x98badcfe; in _cupsMD5Init()
278 pms->abcd[3] = 0x10325476; in _cupsMD5Init()
[all …]
/external/boringssl/src/crypto/fipsmodule/sha/asm/
Dsha512-armv8.pl337 my ($ABCD,$EFGH,$abcd)=map("v$_.16b",(0..2));
372 orr $abcd,$ABCD,$ABCD
374 sha256h2 $EFGH,$abcd,$W0
382 orr $abcd,$ABCD,$ABCD
384 sha256h2 $EFGH,$abcd,$W0
388 orr $abcd,$ABCD,$ABCD
390 sha256h2 $EFGH,$abcd,$W1
395 orr $abcd,$ABCD,$ABCD
397 sha256h2 $EFGH,$abcd,$W0
400 orr $abcd,$ABCD,$ABCD
[all …]
/external/python/cpython2/Modules/
Dmd5.c136 a = pms->abcd[0], b = pms->abcd[1], in md5_process()
137 c = pms->abcd[2], d = pms->abcd[3]; in md5_process()
307 pms->abcd[0] += a; in md5_process()
308 pms->abcd[1] += b; in md5_process()
309 pms->abcd[2] += c; in md5_process()
310 pms->abcd[3] += d; in md5_process()
317 pms->abcd[0] = 0x67452301; in md5_init()
318 pms->abcd[1] = /*0xefcdab89*/ T_MASK ^ 0x10325476; in md5_init()
319 pms->abcd[2] = /*0x98badcfe*/ T_MASK ^ 0x67452301; in md5_init()
320 pms->abcd[3] = 0x10325476; in md5_init()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dh-register-addressing-32.ll13 ; CHECK: movzbl %{{[abcd]}}h, %e
23 ; CHECK: movzbl %{{[abcd]}}h, %e
33 ; CHECK: movzbl %{{[abcd]}}h, %e
43 ; CHECK: movzbl %{{[abcd]}}h, %e
53 ; CHECK: movzbl %{{[abcd]}}h, %e
63 ; CHECK: movzbl %{{[abcd]}}h, %e
73 ; CHECK: movzbl %{{[abcd]}}h, %e
Dh-register-addressing-64.ll13 ; CHECK: movzbl %{{[abcd]}}h, %e
23 ; CHECK: movzbl %{{[abcd]}}h, %e
33 ; CHECK: movzbl %{{[abcd]}}h, %e
43 ; CHECK: movzbl %{{[abcd]}}h, %e
53 ; CHECK: movzbl %{{[abcd]}}h, %e
63 ; CHECK: movzbl %{{[abcd]}}h, %e
73 ; CHECK: movzbl %{{[abcd]}}h, %e
/external/honggfuzz/examples/apache-httpd/corpus_http1/
Dad87e0f6cce06a460ed29c58af5d1be4.00000448.honggfuzz.cov1 PRCON HTTP://[2002:abcd:abcd::1abcd::1abcd::1]Ihx.html HTTP/1.1
/external/honggfuzz/examples/apache-httpd/corpus_http2/
Dad87e0f6cce06a460ed29c58af5d1be4.00000448.honggfuzz.cov1 PRCON HTTP://[2002:abcd:abcd::1abcd::1abcd::1]Ihx.html HTTP/1.1
/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
D8bit.pnacl.ll34 ; CHECK: add {{[abcd]l}}
50 ; CHECK: add {{[abcd]l}}
67 ; CHECK: sub {{[abcd]l}}
83 ; CHECK: sub {{[abcd]l}}
100 ; CHECK: mul {{[abcd]l|BYTE PTR}}
118 ; CHECK: mul {{[abcd]l|BYTE PTR}}
136 ; CHECK: div {{[abcd]l|BYTE PTR}}
153 ; CHECK: div {{[abcd]l|BYTE PTR}}
172 ; CHECK: div {{[abcd]l|BYTE PTR}}
175 ; REM-NEXT: mov {{[abcd]}}l,ah
[all …]

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