/external/llvm/lib/CodeGen/ |
D | ExpandPostRAPseudos.cpp | 128 CopyMI->addRegisterDefined(DstReg); in LowerSubregToReg()
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D | VirtRegMap.cpp | 459 MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI); in rewrite()
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D | MachineInstr.cpp | 2087 void MachineInstr::addRegisterDefined(unsigned Reg, in addRegisterDefined() function in MachineInstr 2127 addRegisterDefined(*I, &TRI); in setPhysRegsDeadExcept()
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D | RegAllocFast.cpp | 707 MI->addRegisterDefined(PhysReg, TRI); in setPhysReg()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
D | ExpandPostRAPseudos.cpp | 124 CopyMI->addRegisterDefined(DstReg); in LowerSubregToReg()
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D | VirtRegMap.cpp | 584 MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI); in rewrite()
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D | MachineInstr.cpp | 1708 void MachineInstr::addRegisterDefined(unsigned Reg, in addRegisterDefined() function in MachineInstr 1748 addRegisterDefined(*I, &TRI); in setPhysRegsDeadExcept()
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D | RegAllocFast.cpp | 724 MI.addRegisterDefined(PhysReg, TRI); in setPhysReg()
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
D | MachineInstr.h | 460 void addRegisterDefined(unsigned IncomingReg,
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
D | ProcessImplicitDefs.cpp | 171 MI->addRegisterDefined(Reg); in runOnMachineFunction()
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D | VirtRegMap.cpp | 326 MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI); in rewrite()
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D | RegisterCoalescer.cpp | 976 UseMI->addRegisterDefined(DstReg, TRI); in UpdateRegDefsUses() 1956 MI->addRegisterDefined(S, TRI); in runOnMachineFunction()
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D | MachineInstr.cpp | 1673 void MachineInstr::addRegisterDefined(unsigned IncomingReg, in addRegisterDefined() function in MachineInstr
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D | LiveIntervalAnalysis.cpp | 312 mi->addRegisterDefined(interval.reg); in handleVirtualRegisterDef()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
D | SparcInstrInfo.cpp | 390 MovMI->addRegisterDefined(DestReg, TRI); in copyPhysReg()
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/external/llvm/include/llvm/CodeGen/ |
D | MachineInstr.h | 1105 void addRegisterDefined(unsigned Reg,
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/external/llvm/lib/Target/Lanai/ |
D | LanaiInstrInfo.cpp | 432 MI->addRegisterDefined(Lanai::SR); in optimizeCompareInstr()
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/external/llvm/lib/Target/Sparc/ |
D | SparcInstrInfo.cpp | 386 MovMI->addRegisterDefined(DestReg, TRI); in copyPhysReg()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
D | LanaiInstrInfo.cpp | 431 MI->addRegisterDefined(Lanai::SR); in optimizeCompareInstr()
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/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
D | MachineInstr.h | 1193 void addRegisterDefined(unsigned Reg,
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
D | X86ISelLowering.cpp | 11981 MI->addRegisterDefined(X86::RSI); in EmitInstrWithCustomInserter() 11982 MI->addRegisterDefined(X86::RDI); in EmitInstrWithCustomInserter() 11983 MI->addRegisterDefined(X86::XMM6); in EmitInstrWithCustomInserter() 11984 MI->addRegisterDefined(X86::XMM7); in EmitInstrWithCustomInserter() 11985 MI->addRegisterDefined(X86::XMM8); in EmitInstrWithCustomInserter() 11986 MI->addRegisterDefined(X86::XMM9); in EmitInstrWithCustomInserter() 11987 MI->addRegisterDefined(X86::XMM10); in EmitInstrWithCustomInserter() 11988 MI->addRegisterDefined(X86::XMM11); in EmitInstrWithCustomInserter() 11989 MI->addRegisterDefined(X86::XMM12); in EmitInstrWithCustomInserter() 11990 MI->addRegisterDefined(X86::XMM13); in EmitInstrWithCustomInserter() [all …]
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMBaseInstrInfo.cpp | 679 Mov->addRegisterDefined(DestReg, TRI); in copyPhysReg()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrInfo.cpp | 1142 MI->addRegisterDefined(AArch64::NZCV, TRI); in substituteCmpToZero()
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/external/llvm/lib/Target/ARM/ |
D | ARMBaseInstrInfo.cpp | 846 Mov->addRegisterDefined(DestReg, TRI); in copyPhysReg()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
D | AArch64InstrInfo.cpp | 1591 MI->addRegisterDefined(AArch64::NZCV, TRI); in substituteCmpToZero()
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