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Searched refs:addRegisterDefined (Results 1 – 25 of 26) sorted by relevance

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/external/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp128 CopyMI->addRegisterDefined(DstReg); in LowerSubregToReg()
DVirtRegMap.cpp459 MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI); in rewrite()
DMachineInstr.cpp2087 void MachineInstr::addRegisterDefined(unsigned Reg, in addRegisterDefined() function in MachineInstr
2127 addRegisterDefined(*I, &TRI); in setPhysRegsDeadExcept()
DRegAllocFast.cpp707 MI->addRegisterDefined(PhysReg, TRI); in setPhysReg()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp124 CopyMI->addRegisterDefined(DstReg); in LowerSubregToReg()
DVirtRegMap.cpp584 MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI); in rewrite()
DMachineInstr.cpp1708 void MachineInstr::addRegisterDefined(unsigned Reg, in addRegisterDefined() function in MachineInstr
1748 addRegisterDefined(*I, &TRI); in setPhysRegsDeadExcept()
DRegAllocFast.cpp724 MI.addRegisterDefined(PhysReg, TRI); in setPhysReg()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DMachineInstr.h460 void addRegisterDefined(unsigned IncomingReg,
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DProcessImplicitDefs.cpp171 MI->addRegisterDefined(Reg); in runOnMachineFunction()
DVirtRegMap.cpp326 MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI); in rewrite()
DRegisterCoalescer.cpp976 UseMI->addRegisterDefined(DstReg, TRI); in UpdateRegDefsUses()
1956 MI->addRegisterDefined(S, TRI); in runOnMachineFunction()
DMachineInstr.cpp1673 void MachineInstr::addRegisterDefined(unsigned IncomingReg, in addRegisterDefined() function in MachineInstr
DLiveIntervalAnalysis.cpp312 mi->addRegisterDefined(interval.reg); in handleVirtualRegisterDef()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp390 MovMI->addRegisterDefined(DestReg, TRI); in copyPhysReg()
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h1105 void addRegisterDefined(unsigned Reg,
/external/llvm/lib/Target/Lanai/
DLanaiInstrInfo.cpp432 MI->addRegisterDefined(Lanai::SR); in optimizeCompareInstr()
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp386 MovMI->addRegisterDefined(DestReg, TRI); in copyPhysReg()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/
DLanaiInstrInfo.cpp431 MI->addRegisterDefined(Lanai::SR); in optimizeCompareInstr()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DMachineInstr.h1193 void addRegisterDefined(unsigned Reg,
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86ISelLowering.cpp11981 MI->addRegisterDefined(X86::RSI); in EmitInstrWithCustomInserter()
11982 MI->addRegisterDefined(X86::RDI); in EmitInstrWithCustomInserter()
11983 MI->addRegisterDefined(X86::XMM6); in EmitInstrWithCustomInserter()
11984 MI->addRegisterDefined(X86::XMM7); in EmitInstrWithCustomInserter()
11985 MI->addRegisterDefined(X86::XMM8); in EmitInstrWithCustomInserter()
11986 MI->addRegisterDefined(X86::XMM9); in EmitInstrWithCustomInserter()
11987 MI->addRegisterDefined(X86::XMM10); in EmitInstrWithCustomInserter()
11988 MI->addRegisterDefined(X86::XMM11); in EmitInstrWithCustomInserter()
11989 MI->addRegisterDefined(X86::XMM12); in EmitInstrWithCustomInserter()
11990 MI->addRegisterDefined(X86::XMM13); in EmitInstrWithCustomInserter()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMBaseInstrInfo.cpp679 Mov->addRegisterDefined(DestReg, TRI); in copyPhysReg()
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp1142 MI->addRegisterDefined(AArch64::NZCV, TRI); in substituteCmpToZero()
/external/llvm/lib/Target/ARM/
DARMBaseInstrInfo.cpp846 Mov->addRegisterDefined(DestReg, TRI); in copyPhysReg()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp1591 MI->addRegisterDefined(AArch64::NZCV, TRI); in substituteCmpToZero()

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