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Searched refs:add_use (Results 1 – 10 of 10) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dshl_add_ptr.ll22 define void @load_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
27 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
42 define void @load_shl_base_lds_1(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
48 store i32 %shl_add_use, i32 addrspace(1)* %add_use, align 4
58 …_base_lds_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %lds, i32 addrspace(1)* %add_use) #0 {
63 store i32 %idx.0, i32 addrspace(1)* %add_use
92 define void @store_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
97 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
107 ; define void @atomic_load_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
113 ; store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
[all …]
Dllvm.amdgcn.atomic.dec.ll243 define void @atomic_dec_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
248 store i32 %idx.0, i32 addrspace(1)* %add_use
366 define void @atomic_dec_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
371 store i32 %idx.0, i32 addrspace(1)* %add_use
Dllvm.amdgcn.atomic.inc.ll118 define void @atomic_inc_shl_base_lds_0_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
123 store i32 %idx.0, i32 addrspace(1)* %add_use
300 define void @atomic_inc_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
305 store i32 %idx.0, i32 addrspace(1)* %add_use
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dshl_add_ptr.ll22 define amdgpu_kernel void @load_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %add_use…
27 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
42 define amdgpu_kernel void @load_shl_base_lds_1(float addrspace(1)* %out, i32 addrspace(1)* %add_use…
48 store i32 %shl_add_use, i32 addrspace(1)* %add_use, align 4
58 …_base_lds_max_offset(i8 addrspace(1)* %out, i8 addrspace(3)* %lds, i32 addrspace(1)* %add_use) #0 {
63 store i32 %idx.0, i32 addrspace(1)* %add_use
92 …amdgpu_kernel void @store_shl_base_lds_0(float addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
97 store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
107 …pu_kernel void @atomic_load_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
113 ; store i32 %idx.0, i32 addrspace(1)* %add_use, align 4
[all …]
Dllvm.amdgcn.atomic.inc.ll136 …kernel void @atomic_inc_shl_base_lds_0_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
141 store i32 %idx.0, i32 addrspace(1)* %add_use
330 …kernel void @atomic_inc_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
335 store i32 %idx.0, i32 addrspace(1)* %add_use
Dllvm.amdgcn.atomic.dec.ll301 …gpu_kernel void @atomic_dec_shl_base_lds_0(i32 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
306 store i32 %idx.0, i32 addrspace(1)* %add_use
445 …kernel void @atomic_dec_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
450 store i32 %idx.0, i32 addrspace(1)* %add_use
/external/mesa3d/src/gallium/drivers/r600/sb/
Dsb_def_use.cpp116 v->rel->add_use(n); in process_uses()
124 v->add_use(n); in process_uses()
127 v->add_use(n); in process_uses()
136 v->rel->add_use(n); in process_uses()
143 v->add_use(n); in process_uses()
148 n->pred->add_use(n); in process_uses()
153 i->cond->add_use(i); in process_uses()
Dsb_valtable.cpp218 void value::add_use(node* n) { in add_use() function in r600_sb::value
Dsb_ir.h578 void add_use(node *n);
/external/python/cpython2/Lib/compiler/
Dsymbols.py48 def add_use(self, name): member in Scope
319 scope.add_use(node.name)