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Searched refs:addiur2 (Results 1 – 25 of 25) sorted by relevance

/external/llvm/test/MC/Mips/
Dmicromips-16-bit-instructions.s35 # CHECK-EL: addiur2 $6, $7, -1 # encoding: [0x7e,0x6f]
36 # CHECK-EL: addiur2 $6, $7, 12 # encoding: [0x76,0x6f]
90 # CHECK-EB: addiur2 $6, $7, -1 # encoding: [0x6f,0x7e]
91 # CHECK-EB: addiur2 $6, $7, 12 # encoding: [0x6f,0x76]
143 addiur2 $6, $7, -1
144 addiur2 $6, $7, 12
Dmicromips-invalid.s20 addiur2 $9, $7, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
21 addiur2 $6, $7, 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/
Dmicromips-16-bit-instructions.s35 # CHECK-EL: addiur2 $6, $7, -1 # encoding: [0x7e,0x6f]
36 # CHECK-EL: addiur2 $6, $7, 12 # encoding: [0x76,0x6f]
90 # CHECK-EB: addiur2 $6, $7, -1 # encoding: [0x6f,0x7e]
91 # CHECK-EB: addiur2 $6, $7, 12 # encoding: [0x6f,0x76]
143 addiur2 $6, $7, -1
144 addiur2 $6, $7, 12
Dmicromips-invalid.s20 addiur2 $9, $7, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
21 addiur2 $6, $7, 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dadd.ll197 ; MM32: addiur2 $[[T0:[0-9]+]], $4, 4
200 ; MM64: addiur2 $[[T0:[0-9]+]], $4, 4
218 ; MM32: addiur2 $[[T0:[0-9]+]], $4, 4
221 ; MM64: addiur2 $[[T0:[0-9]+]], $4, 4
235 ; MM32: addiur2 $2, $4, 4
237 ; MM64: addiur2 $2, $4, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/llvm-ir/
Dadd.ll251 ; MM32: addiur2 $[[T0:[0-9]+]], $4, 4
269 ; MM32: addiur2 $[[T0:[0-9]+]], $4, 4
283 ; MM32: addiur2 $2, $4, 4
296 ; MM32: addiur2 $[[T1:[0-9]+]], $5, 4
342 ; MMR3: addiur2 $[[T0:[0-9]+]], $7, 4
351 ; MMR6: addiur2 $[[T1:[0-9]+]], $7, 4
379 ; MMR6: addiur2 $[[T0:[0-9]+]], $4, 1
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dmicromips-addiu.ll32 ; CHECK: addiur2 ${{[2-7]|16|17}}, ${{[2-7]|16|17}}, 24
/external/llvm/test/CodeGen/Mips/
Dmicromips-addiu.ll32 ; CHECK: addiur2 ${{[2-7]|16|17}}, ${{[2-7]|16|17}}, 24
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/micromips/
Dvalid.s70 addiur2 $6, $7, -1 # CHECK: addiur2 $6, $7, -1 # encoding: [0x6f,0x7e] label
72 addiur2 $6, $7, 12 # CHECK: addiur2 $6, $7, 12 # encoding: [0x6f,0x76] label
/external/llvm/test/MC/Mips/micromips64r6/
Dvalid.s5 addiur2 $6, $7, -1 # CHECK: addiur2 $6, $7, -1 # encoding: [0x6f,0x7e]
6 addiur2 $6, $7, 12 # CHECK: addiur2 $6, $7, 12 # encoding: [0x6f,0x76]
Dinvalid.s7 addiur2 $9, $7, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
8 …addiur2 $6, $7, 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of ran…
/external/llvm/test/MC/Mips/micromips32r6/
Dvalid.s9 addiur2 $6, $7, -1 # CHECK: addiur2 $6, $7, -1 # encoding: [0x6f,0x7e]
10 addiur2 $6, $7, 12 # CHECK: addiur2 $6, $7, 12 # encoding: [0x6f,0x76]
Dinvalid.s7 addiur2 $9, $7, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
8 …addiur2 $6, $7, 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of ran…
/external/llvm/test/MC/Disassembler/Mips/micromips32r3/
Dvalid-el.txt37 0x7e 0x6f # CHECK: addiur2 $6, $7, -1
38 0x76 0x6f # CHECK: addiur2 $6, $7, 12
Dvalid.txt37 0x6f 0x7e # CHECK: addiur2 $6, $7, -1
38 0x6f 0x76 # CHECK: addiur2 $6, $7, 12
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/micromips32r6/
Dvalid.s10 addiur2 $6, $7, -1 # CHECK: addiur2 $6, $7, -1 # encoding: [0x6f,0x7e]
12 addiur2 $6, $7, 12 # CHECK: addiur2 $6, $7, 12 # encoding: [0x6f,0x76]
Dinvalid.s7 addiur2 $9, $7, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
8 …addiur2 $6, $7, 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of ran…
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/micromips32r3/
Dvalid-el.txt38 0x7e 0x6f # CHECK: addiur2 $6, $7, -1
39 0x76 0x6f # CHECK: addiur2 $6, $7, 12
Dvalid.txt38 0x6f 0x7e # CHECK: addiur2 $6, $7, -1
39 0x6f 0x76 # CHECK: addiur2 $6, $7, 12
/external/llvm/test/MC/Disassembler/Mips/micromips64r6/
Dvalid.txt4 0x6f 0x7e # CHECK: addiur2 $6, $7, -1
5 0x6f 0x76 # CHECK: addiur2 $6, $7, 12
/external/llvm/test/MC/Disassembler/Mips/micromips32r6/
Dvalid.txt4 0x6f 0x7e # CHECK: addiur2 $6, $7, -1
5 0x6f 0x76 # CHECK: addiur2 $6, $7, 12
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/micromips32r6/
Dvalid.txt4 0x6f 0x7e # CHECK: addiur2 $6, $7, -1
5 0x6f 0x76 # CHECK: addiur2 $6, $7, 12
/external/llvm/lib/Target/Mips/
DMicroMipsInstrInfo.td633 def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMicroMipsInstrInfo.td674 def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16,
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenAsmMatcher.inc4835 "diu\007addiupc\taddiur1sp\007addiur2\007addius5\007addiusp\007addq.ph\t"
5102 …{ 122 /* addiur2 */, Mips::ADDIUR2_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Featur…
7943 { Feature_InMicroMips, 122 /* addiur2 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ },