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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-neon-add-pairwise.ll3 declare <8 x i8> @llvm.aarch64.neon.addp.v8i8(<8 x i8>, <8 x i8>)
8 %tmp1 = call <8 x i8> @llvm.aarch64.neon.addp.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
9 ; CHECK: addp v0.8b, v0.8b, v1.8b
13 declare <16 x i8> @llvm.aarch64.neon.addp.v16i8(<16 x i8>, <16 x i8>)
17 %tmp1 = call <16 x i8> @llvm.aarch64.neon.addp.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
18 ; CHECK: addp v0.16b, v0.16b, v1.16b
22 declare <4 x i16> @llvm.aarch64.neon.addp.v4i16(<4 x i16>, <4 x i16>)
26 %tmp1 = call <4 x i16> @llvm.aarch64.neon.addp.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
27 ; CHECK: addp v0.4h, v0.4h, v1.4h
31 declare <8 x i16> @llvm.aarch64.neon.addp.v8i16(<8 x i16>, <8 x i16>)
[all …]
Darm64-vadd.ll641 ;CHECK: addp.8b
644 %tmp3 = call <8 x i8> @llvm.aarch64.neon.addp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
650 ;CHECK: addp.16b
653 %tmp3 = call <16 x i8> @llvm.aarch64.neon.addp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
659 ;CHECK: addp.4h
662 %tmp3 = call <4 x i16> @llvm.aarch64.neon.addp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
668 ;CHECK: addp.8h
671 %tmp3 = call <8 x i16> @llvm.aarch64.neon.addp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
677 ;CHECK: addp.2s
680 %tmp3 = call <2 x i32> @llvm.aarch64.neon.addp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
[all …]
Darm64-vaddv.ll52 ; CHECK: addp.2s v[[REGNUM:[0-9]+]], v0, v0
62 ; CHECK: addp.2s v[[REGNUM:[0-9]+]], v1, v1
73 ; CHECK: addp.2d [[REGNUM:d[0-9]+]], v0
83 ; CHECK: addp.2d d[[REGNUM:[0-9]+]], v1
163 ; CHECK: addp.2s v[[REGNUM:[0-9]+]], v0, v0
173 ; CHECK: addp.2s v[[REGNUM:[0-9]+]], v1, v1
212 ; CHECK: addp.2d [[REGNUM:d[0-9]+]], v0
222 ; CHECK: addp.2d d[[REGNUM:[0-9]+]], v1
233 ; CHECK: addp.2d d0, v0
/external/llvm/test/CodeGen/AArch64/
Darm64-neon-add-pairwise.ll3 declare <8 x i8> @llvm.aarch64.neon.addp.v8i8(<8 x i8>, <8 x i8>)
8 %tmp1 = call <8 x i8> @llvm.aarch64.neon.addp.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
9 ; CHECK: addp v0.8b, v0.8b, v1.8b
13 declare <16 x i8> @llvm.aarch64.neon.addp.v16i8(<16 x i8>, <16 x i8>)
17 %tmp1 = call <16 x i8> @llvm.aarch64.neon.addp.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
18 ; CHECK: addp v0.16b, v0.16b, v1.16b
22 declare <4 x i16> @llvm.aarch64.neon.addp.v4i16(<4 x i16>, <4 x i16>)
26 %tmp1 = call <4 x i16> @llvm.aarch64.neon.addp.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
27 ; CHECK: addp v0.4h, v0.4h, v1.4h
31 declare <8 x i16> @llvm.aarch64.neon.addp.v8i16(<8 x i16>, <8 x i16>)
[all …]
Darm64-vadd.ll641 ;CHECK: addp.8b
644 %tmp3 = call <8 x i8> @llvm.aarch64.neon.addp.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
650 ;CHECK: addp.16b
653 %tmp3 = call <16 x i8> @llvm.aarch64.neon.addp.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
659 ;CHECK: addp.4h
662 %tmp3 = call <4 x i16> @llvm.aarch64.neon.addp.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
668 ;CHECK: addp.8h
671 %tmp3 = call <8 x i16> @llvm.aarch64.neon.addp.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
677 ;CHECK: addp.2s
680 %tmp3 = call <2 x i32> @llvm.aarch64.neon.addp.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
[all …]
Darm64-vaddv.ll52 ; CHECK: addp.2s v[[REGNUM:[0-9]+]], v0, v0
62 ; CHECK: addp.2s v[[REGNUM:[0-9]+]], v1, v1
73 ; CHECK: addp.2d [[REGNUM:d[0-9]+]], v0
83 ; CHECK: addp.2d d[[REGNUM:[0-9]+]], v1
163 ; CHECK: addp.2s v[[REGNUM:[0-9]+]], v0, v0
173 ; CHECK: addp.2s v[[REGNUM:[0-9]+]], v1, v1
212 ; CHECK: addp.2d [[REGNUM:d[0-9]+]], v0
222 ; CHECK: addp.2d d[[REGNUM:[0-9]+]], v1
233 ; CHECK: addp.2d d0, v0
/external/capstone/suite/MC/AArch64/
Dneon-add-pairwise.s.cs2 0x20,0xbc,0x22,0x0e = addp v0.8b, v1.8b, v2.8b
3 0x20,0xbc,0x22,0x4e = addp v0.16b, v1.16b, v2.16b
4 0x20,0xbc,0x62,0x0e = addp v0.4h, v1.4h, v2.4h
5 0x20,0xbc,0x62,0x4e = addp v0.8h, v1.8h, v2.8h
6 0x20,0xbc,0xa2,0x0e = addp v0.2s, v1.2s, v2.2s
7 0x20,0xbc,0xa2,0x4e = addp v0.4s, v1.4s, v2.4s
8 0x20,0xbc,0xe2,0x4e = addp v0.2d, v1.2d, v2.2d
Dneon-scalar-reduce-pairwise.s.cs2 0x20,0xb8,0xf1,0x5e = addp d0, v1.2d
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-add-pairwise.s9 addp v0.8b, v1.8b, v2.8b
10 addp v0.16b, v1.16b, v2.16b
11 addp v0.4h, v1.4h, v2.4h
12 addp v0.8h, v1.8h, v2.8h
13 addp v0.2s, v1.2s, v2.2s
14 addp v0.4s, v1.4s, v2.4s
15 addp v0.2d, v1.2d, v2.2d
Dneon-scalar-reduce-pairwise.s6 addp d0, v1.2d define
/external/llvm/test/MC/AArch64/
Dneon-add-pairwise.s9 addp v0.8b, v1.8b, v2.8b
10 addp v0.16b, v1.16b, v2.16b
11 addp v0.4h, v1.4h, v2.4h
12 addp v0.8h, v1.8h, v2.8h
13 addp v0.2s, v1.2s, v2.2s
14 addp v0.4s, v1.4s, v2.4s
15 addp v0.2d, v1.2d, v2.2d
Ddirective-cpu.s17 addp v0.4s, v0.4s, v0.4s
21 addp v0.4s, v0.4s, v0.4s
Dneon-scalar-reduce-pairwise.s6 addp d0, v1.2d define
/external/libavc/common/armv8/
Dih264_intra_pred_chroma_av8.s132 addp v0.4s, v0.4s , v0.4s
133 addp v1.4s, v1.4s , v1.4s
134 addp v0.4s, v0.4s , v0.4s
135 addp v1.4s, v1.4s , v1.4s
138 addp v2.4s, v2.4s , v2.4s
139 addp v3.4s, v3.4s , v3.4s
140 addp v2.4s, v2.4s , v2.4s
141 addp v3.4s, v3.4s , v3.4s
159 addp v0.4s, v0.4s , v0.4s
160 addp v1.4s, v1.4s , v1.4s
[all …]
Dih264_resi_trans_quant_av8.s220 addp v0.8b, v0.8b, v0.8b //i pair add nnz 1
221 addp v0.8b, v0.8b, v0.8b //i pair add nnz 1
222 addp v0.8b, v0.8b, v0.8b //i pair add nnz 1
422 addp v0.8b, v0.8b, v0.8b //i pair add nnz 1
423 addp v0.8b, v0.8b, v0.8b //i pair add nnz 1
424 addp v0.8b, v0.8b, v0.8b //i pair add nnz 1
573 addp v2.8b, v2.8b, v2.8b
574 addp v2.8b, v2.8b, v2.8b
575 addp v2.8b, v2.8b, v2.8b
674 addp v5.8b, v5.8b, v5.8b //sum up nnz
[all …]
/external/libavc/encoder/armv8/
Dih264e_evaluate_intra_chroma_modes_av8.s119 addp v0.4s, v0.4s , v0.4s
120 addp v1.4s, v1.4s , v1.4s
121 addp v0.4s, v0.4s , v0.4s
122 addp v1.4s, v1.4s , v1.4s
125 addp v2.4s, v2.4s , v2.4s
126 addp v3.4s, v3.4s , v3.4s
127 addp v2.4s, v2.4s , v2.4s
128 addp v3.4s, v3.4s , v3.4s
150 addp v0.4s, v0.4s , v0.4s
151 addp v1.4s, v1.4s , v1.4s
[all …]
Dime_distortion_metrics_av8.s134 addp v30.8h, v30.8h, v30.8h
136 addp v30.2s, v30.2s, v30.2s
217 addp v30.8h, v30.8h, v30.8h
219 addp v30.2s, v30.2s, v30.2s
313 addp v31.8h, v30.8h, v30.8h
315 addp v31.2s, v31.2s, v31.2s
362 addp v31.8h, v30.8h, v30.8h
364 addp v31.2s, v31.2s, v31.2s
443 addp v30.8h, v30.8h, v31.8h
445 addp v30.2s, v30.2s, v30.2s
[all …]
/external/libmpeg2/common/armv8/
Dicv_variance_av8.s81 addp v4.8h, v4.8h, v4.8h
82 addp v4.4h, v4.4h, v4.4h
83 addp v4.4h, v4.4h, v4.4h
99 addp v20.4s, v20.4s, v20.4s
100 addp v20.2s, v20.2s, v20.2s
Dicv_sad_av8.s94 addp v0.8h, v0.8h, v0.8h
95 addp v0.8h, v0.8h, v0.8h
96 addp v0.8h, v0.8h, v0.8h
Dideint_spatial_filter_av8.s125 addp v16.8h, v16.8h, v16.8h
126 addp v18.8h, v18.8h, v18.8h
127 addp v20.8h, v20.8h, v20.8h
/external/v8/src/regexp/x64/
Dregexp-macro-assembler-x64.cc145 __ addp(register_location(reg), Immediate(by)); in AdvanceRegister() local
154 __ addp(rbx, code_object_pointer()); in Backtrack() local
249 __ addp(rbx, r9); // End of capture in CheckNotBackReferenceIgnoreCase() local
282 __ addp(r11, Immediate(1)); in CheckNotBackReferenceIgnoreCase() local
283 __ addp(r9, Immediate(1)); in CheckNotBackReferenceIgnoreCase() local
416 __ addp(rdx, rsi); // Start of capture. in CheckNotBackReference() local
436 __ addp(rbx, Immediate(char_size())); in CheckNotBackReference() local
437 __ addp(rdx, Immediate(char_size())); in CheckNotBackReference() local
836 __ addp(rcx, rdx); in GetCode() local
844 __ addp(rax, rcx); // Convert to index from start, not end. in GetCode() local
[all …]
/external/v8/src/x64/
Ddeoptimizer-x64.cc139 __ addp(rsp, Immediate(kFloatRegsSize)); in Generate() local
149 __ addp(rsp, Immediate(1 * kRegisterSize + kPCOnStackSize)); in Generate() local
154 __ addp(rcx, rsp); in Generate() local
165 __ addp(rdx, Immediate(sizeof(intptr_t))); in Generate() local
203 __ addp(rax, Immediate(kPointerSize)); in Generate() local
/external/llvm/test/CodeGen/Hexagon/
Dbit-gen-rseq.ll21 …%0 = tail call i64 @llvm.hexagon.A2.addp(i64 %t.sroa.0.0.insert.insert, i64 %t.sroa.0.0.insert.ins…
34 …%1 = tail call i64 @llvm.hexagon.A2.addp(i64 %t.sroa.0.0.insert.insert19, i64 %t.sroa.0.0.insert.i…
40 declare i64 @llvm.hexagon.A2.addp(i64, i64) #1
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dbit-gen-rseq.ll21 …%0 = tail call i64 @llvm.hexagon.A2.addp(i64 %t.sroa.0.0.insert.insert, i64 %t.sroa.0.0.insert.ins…
34 …%1 = tail call i64 @llvm.hexagon.A2.addp(i64 %t.sroa.0.0.insert.insert19, i64 %t.sroa.0.0.insert.i…
40 declare i64 @llvm.hexagon.A2.addp(i64, i64) #1
Dearly-if-merge-loop.ll33 %v21 = tail call i64 @llvm.hexagon.A2.addp(i64 %v20, i64 %v5)
40 %v28 = tail call i64 @llvm.hexagon.A2.addp(i64 %v27, i64 %v5)
75 %v59 = tail call i64 @llvm.hexagon.A2.addp(i64 %v57, i64 %v58)
81 declare i64 @llvm.hexagon.A2.addp(i64, i64) #1

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