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/external/llvm/test/CodeGen/Mips/msa/
Dspill.ll76 %r1 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %1)
77 %r2 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r1, <16 x i8> %2)
78 %r3 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r2, <16 x i8> %3)
79 %r4 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r3, <16 x i8> %4)
80 %r5 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r4, <16 x i8> %5)
81 %r6 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r5, <16 x i8> %6)
82 %r7 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r6, <16 x i8> %7)
83 %r8 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r7, <16 x i8> %8)
84 %r9 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r8, <16 x i8> %9)
85 %r10 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r9, <16 x i8> %10)
[all …]
Dbitcast.ll9 %1 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %0)
11 %3 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %2, <16 x i8> %2)
18 ; LITENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
19 ; LITENDIAN: addv.b [[R3:\$w[0-9]+]], [[R2]], [[R2]]
25 ; BIGENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
26 ; BIGENDIAN: addv.b [[R3:\$w[0-9]+]], [[R2]], [[R2]]
33 %1 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %0)
35 %3 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %2, <8 x i16> %2)
42 ; LITENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
43 ; LITENDIAN: addv.h [[R3:\$w[0-9]+]], [[R2]], [[R2]]
[all …]
Dbasic_operations.ll297 ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
315 ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
333 ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
348 ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
367 ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
384 ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
401 ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
416 ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
437 ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
464 ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
[all …]
D3r-a.ll420 %2 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %1)
425 declare <16 x i8> @llvm.mips.addv.b(<16 x i8>, <16 x i8>) nounwind
432 ; CHECK-DAG: addv.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]
445 %2 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %1)
450 declare <8 x i16> @llvm.mips.addv.h(<8 x i16>, <8 x i16>) nounwind
457 ; CHECK-DAG: addv.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]
470 %2 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %1)
475 declare <4 x i32> @llvm.mips.addv.w(<4 x i32>, <4 x i32>) nounwind
482 ; CHECK-DAG: addv.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]
495 %2 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %1)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/msa/
Dspill.ll76 %r1 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %1)
77 %r2 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r1, <16 x i8> %2)
78 %r3 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r2, <16 x i8> %3)
79 %r4 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r3, <16 x i8> %4)
80 %r5 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r4, <16 x i8> %5)
81 %r6 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r5, <16 x i8> %6)
82 %r7 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r6, <16 x i8> %7)
83 %r8 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r7, <16 x i8> %8)
84 %r9 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r8, <16 x i8> %9)
85 %r10 = call <16 x i8> @llvm.mips.addv.b(<16 x i8> %r9, <16 x i8> %10)
[all …]
Dbitcast.ll9 %1 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %0)
11 %3 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %2, <16 x i8> %2)
18 ; LITENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
19 ; LITENDIAN: addv.b [[R3:\$w[0-9]+]], [[R2]], [[R2]]
25 ; BIGENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
26 ; BIGENDIAN: addv.b [[R3:\$w[0-9]+]], [[R2]], [[R2]]
33 %1 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %0)
35 %3 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %2, <8 x i16> %2)
42 ; LITENDIAN: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
43 ; LITENDIAN: addv.h [[R3:\$w[0-9]+]], [[R2]], [[R2]]
[all …]
Dbasic_operations.ll328 ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
346 ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
364 ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
379 ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
398 ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
415 ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
432 ; ALL-DAG: addv.w [[R2:\$w[0-9]+]], [[R1]], [[R1]]
447 ; ALL-DAG: addv.d [[R2:\$w[0-9]+]], [[R1]], [[R1]]
468 ; ALL-DAG: addv.b [[R2:\$w[0-9]+]], [[R1]], [[R1]]
495 ; ALL-DAG: addv.h [[R2:\$w[0-9]+]], [[R1]], [[R1]]
[all …]
D3r-a.ll420 %2 = tail call <16 x i8> @llvm.mips.addv.b(<16 x i8> %0, <16 x i8> %1)
425 declare <16 x i8> @llvm.mips.addv.b(<16 x i8>, <16 x i8>) nounwind
432 ; CHECK-DAG: addv.b [[WD:\$w[0-9]+]], [[WS]], [[WT]]
445 %2 = tail call <8 x i16> @llvm.mips.addv.h(<8 x i16> %0, <8 x i16> %1)
450 declare <8 x i16> @llvm.mips.addv.h(<8 x i16>, <8 x i16>) nounwind
457 ; CHECK-DAG: addv.h [[WD:\$w[0-9]+]], [[WS]], [[WT]]
470 %2 = tail call <4 x i32> @llvm.mips.addv.w(<4 x i32> %0, <4 x i32> %1)
475 declare <4 x i32> @llvm.mips.addv.w(<4 x i32>, <4 x i32>) nounwind
482 ; CHECK-DAG: addv.w [[WD:\$w[0-9]+]], [[WS]], [[WT]]
495 %2 = tail call <2 x i64> @llvm.mips.addv.d(<2 x i64> %0, <2 x i64> %1)
[all …]
/external/capstone/suite/MC/AArch64/
Dneon-across.s.cs32 0x20,0xb8,0x31,0x0e = addv b0, v1.8b
33 0x20,0xb8,0x31,0x4e = addv b0, v1.16b
34 0x20,0xb8,0x71,0x0e = addv h0, v1.4h
35 0x20,0xb8,0x71,0x4e = addv h0, v1.8h
36 0x20,0xb8,0xb1,0x4e = addv s0, v1.4s
/external/llvm/test/MC/AArch64/
Dneon-across.s81 addv b0, v1.8b
82 addv b0, v1.16b
83 addv h0, v1.4h
84 addv h0, v1.8h
85 addv s0, v1.4s
Ddot-req.s28 addv bob, v0.8b
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-across.s81 addv b0, v1.8b
82 addv b0, v1.16b
83 addv h0, v1.4h
84 addv h0, v1.8h
85 addv s0, v1.4s
Ddot-req.s28 addv bob, v0.8b
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-vaddv.ll5 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
16 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1
28 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0
39 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1
94 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
105 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1
117 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
128 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0
139 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1
151 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0
[all …]
Daarch64-addv.ll11 ; CHECK: addv {{b[0-9]+}}, {{v[0-9]+}}.16b
19 ; CHECK: addv {{h[0-9]+}}, {{v[0-9]+}}.8h
27 ; CHECK: addv {{s[0-9]+}}, {{v[0-9]+}}.4s
35 ; CHECK-NOT: addv
45 ; CHECK: addv {{s[0-9]+}}, {{v[0-9]+}}.4s
65 ; CHECK: addv {{s[0-9]+}}, {{v[0-9]+}}.4s
Darm64-neon-across.ll343 ; CHECK: addv b{{[0-9]+}}, {{v[0-9]+}}.8b
352 ; CHECK: addv h{{[0-9]+}}, {{v[0-9]+}}.4h
361 ; CHECK: addv b{{[0-9]+}}, {{v[0-9]+}}.8b
370 ; CHECK: addv h{{[0-9]+}}, {{v[0-9]+}}.4h
379 ; CHECK: addv b{{[0-9]+}}, {{v[0-9]+}}.16b
388 ; CHECK: addv h{{[0-9]+}}, {{v[0-9]+}}.8h
397 ; CHECK: addv s{{[0-9]+}}, {{v[0-9]+}}.4s
405 ; CHECK: addv b{{[0-9]+}}, {{v[0-9]+}}.16b
414 ; CHECK: addv h{{[0-9]+}}, {{v[0-9]+}}.8h
423 ; CHECK: addv s{{[0-9]+}}, {{v[0-9]+}}.4s
/external/llvm/test/CodeGen/AArch64/
Darm64-vaddv.ll5 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
16 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1
28 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0
39 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1
94 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
105 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1
117 ; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0
128 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0
139 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1
151 ; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0
[all …]
Daarch64-addv.ll5 ; CHECK: addv {{b[0-9]+}}, {{v[0-9]+}}.16b
21 ; CHECK: addv {{h[0-9]+}}, {{v[0-9]+}}.8h
35 ; CHECK: addv {{s[0-9]+}}, {{v[0-9]+}}.4s
47 ; CHECK-NOT: addv
57 ; CHECK: addv {{s[0-9]+}}, {{v[0-9]+}}.4s
81 ; CHECK: addv {{s[0-9]+}}, {{v[0-9]+}}.4s
Darm64-neon-across.ll343 ; CHECK: addv b{{[0-9]+}}, {{v[0-9]+}}.8b
352 ; CHECK: addv h{{[0-9]+}}, {{v[0-9]+}}.4h
361 ; CHECK: addv b{{[0-9]+}}, {{v[0-9]+}}.8b
370 ; CHECK: addv h{{[0-9]+}}, {{v[0-9]+}}.4h
379 ; CHECK: addv b{{[0-9]+}}, {{v[0-9]+}}.16b
388 ; CHECK: addv h{{[0-9]+}}, {{v[0-9]+}}.8h
397 ; CHECK: addv s{{[0-9]+}}, {{v[0-9]+}}.4s
405 ; CHECK: addv b{{[0-9]+}}, {{v[0-9]+}}.16b
414 ; CHECK: addv h{{[0-9]+}}, {{v[0-9]+}}.8h
423 ; CHECK: addv s{{[0-9]+}}, {{v[0-9]+}}.4s
/external/llvm/test/CodeGen/SystemZ/
Dint-add-16.ll17 %addv = bitcast i128 %add to <2 x i64>
18 %high = extractelement <2 x i64> %addv, i32 0
20 %low = extractelement <2 x i64> %addv, i32 1
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dint-add-16.ll17 %addv = bitcast i128 %add to <2 x i64>
18 %high = extractelement <2 x i64> %addv, i32 0
20 %low = extractelement <2 x i64> %addv, i32 1
/external/capstone/suite/MC/Mips/
Dtest_3r.s.cs18 0x78,0x15,0xa6,0x0e = addv.b $w24, $w20, $w21
19 0x78,0x3b,0x69,0x0e = addv.h $w4, $w13, $w27
20 0x78,0x4e,0x5c,0xce = addv.w $w19, $w11, $w14
21 0x78,0x7f,0xa8,0x8e = addv.d $w2, $w21, $w31
/external/llvm/test/MC/Mips/msa/
Dtest_3r.s19 # CHECK: addv.b $w24, $w20, $w21 # encoding: [0x78,0x15,0xa6,0x0e]
20 # CHECK: addv.h $w4, $w13, $w27 # encoding: [0x78,0x3b,0x69,0x0e]
21 # CHECK: addv.w $w19, $w11, $w14 # encoding: [0x78,0x4e,0x5c,0xce]
22 # CHECK: addv.d $w2, $w21, $w31 # encoding: [0x78,0x7f,0xa8,0x8e]
262 addv.b $w24, $w20, $w21
263 addv.h $w4, $w13, $w27
264 addv.w $w19, $w11, $w14
265 addv.d $w2, $w21, $w31
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/msa/
Dtest_3r.s19 # CHECK: addv.b $w24, $w20, $w21 # encoding: [0x78,0x15,0xa6,0x0e]
20 # CHECK: addv.h $w4, $w13, $w27 # encoding: [0x78,0x3b,0x69,0x0e]
21 # CHECK: addv.w $w19, $w11, $w14 # encoding: [0x78,0x4e,0x5c,0xce]
22 # CHECK: addv.d $w2, $w21, $w31 # encoding: [0x78,0x7f,0xa8,0x8e]
262 addv.b $w24, $w20, $w21
263 addv.h $w4, $w13, $w27
264 addv.w $w19, $w11, $w14
265 addv.d $w2, $w21, $w31
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/AArch64/
Dvector-reduce.ll7 ; CODE: addv b0, v0.8b
16 ; CODE: addv b0, v0.16b
25 ; CODE: addv h0, v0.4h
34 ; CODE: addv h0, v0.8h
43 ; CODE: addv s0, v0.4s

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