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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2014 Freescale Semiconductor, Inc.
4  */
5 
6 #ifndef __ASM_ARCH_LS102XA_IMMAP_H_
7 #define __ASM_ARCH_LS102XA_IMMAP_H_
8 #include <fsl_immap.h>
9 
10 #define SVR_MAJ(svr)		(((svr) >>  4) & 0xf)
11 #define SVR_MIN(svr)		(((svr) >>  0) & 0xf)
12 #define SVR_SOC_VER(svr)	(((svr) >> 8) & 0x7ff)
13 #define IS_E_PROCESSOR(svr)	(svr & 0x80000)
14 #define IS_SVR_REV(svr, maj, min) \
15 		((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min))
16 
17 #define SOC_VER_SLS1020		0x00
18 #define SOC_VER_LS1020		0x10
19 #define SOC_VER_LS1021		0x11
20 #define SOC_VER_LS1022		0x12
21 
22 #define SOC_MAJOR_VER_1_0	0x1
23 #define SOC_MAJOR_VER_2_0	0x2
24 
25 #define CCSR_BRR_OFFSET		0xe4
26 #define CCSR_SCRATCHRW1_OFFSET	0x200
27 
28 #define RCWSR0_SYS_PLL_RAT_SHIFT	25
29 #define RCWSR0_SYS_PLL_RAT_MASK		0x1f
30 #define RCWSR0_MEM_PLL_RAT_SHIFT	16
31 #define RCWSR0_MEM_PLL_RAT_MASK		0x3f
32 
33 #define RCWSR4_SRDS1_PRTCL_SHIFT	24
34 #define RCWSR4_SRDS1_PRTCL_MASK		0xff000000
35 
36 #define TIMER_COMP_VAL			0xffffffffffffffffull
37 #define ARCH_TIMER_CTRL_ENABLE		(1 << 0)
38 #define SYS_COUNTER_CTRL_ENABLE		(1 << 24)
39 
40 #define DCFG_CCSR_PORSR1_RCW_MASK	0xff800000
41 #define DCFG_CCSR_PORSR1_RCW_SRC_I2C	0x24800000
42 
43 #define DCFG_DCSR_PORCR1		0
44 
45 /*
46  * Define default values for some CCSR macros to make header files cleaner
47  *
48  * To completely disable CCSR relocation in a board header file, define
49  * CONFIG_SYS_CCSR_DO_NOT_RELOCATE.  This will force CONFIG_SYS_CCSRBAR_PHYS
50  * to a value that is the same as CONFIG_SYS_CCSRBAR.
51  */
52 
53 #ifdef CONFIG_SYS_CCSRBAR_PHYS
54 #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly."
55 #endif
56 
57 #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
58 #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
59 #undef CONFIG_SYS_CCSRBAR_PHYS_LOW
60 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
61 #endif
62 
63 #ifndef CONFIG_SYS_CCSRBAR
64 #define CONFIG_SYS_CCSRBAR		CONFIG_SYS_IMMR
65 #endif
66 
67 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
68 #ifdef CONFIG_PHYS_64BIT
69 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0xf
70 #else
71 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
72 #endif
73 #endif
74 
75 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
76 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_IMMR
77 #endif
78 
79 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
80 				 CONFIG_SYS_CCSRBAR_PHYS_LOW)
81 
82 struct sys_info {
83 	unsigned long freq_processor[CONFIG_MAX_CPUS];
84 	unsigned long freq_systembus;
85 	unsigned long freq_ddrbus;
86 	unsigned long freq_localbus;
87 };
88 
89 /* Device Configuration and Pin Control */
90 struct ccsr_gur {
91 	u32     porsr1;         /* POR status 1 */
92 	u32     porsr2;         /* POR status 2 */
93 	u8      res_008[0x20-0x8];
94 	u32     gpporcr1;       /* General-purpose POR configuration */
95 	u32	gpporcr2;
96 	u32     dcfg_fusesr;    /* Fuse status register */
97 	u8      res_02c[0x70-0x2c];
98 	u32     devdisr;        /* Device disable control */
99 	u32     devdisr2;       /* Device disable control 2 */
100 	u32     devdisr3;       /* Device disable control 3 */
101 	u32     devdisr4;       /* Device disable control 4 */
102 	u32     devdisr5;       /* Device disable control 5 */
103 	u8      res_084[0x94-0x84];
104 	u32     coredisru;      /* uppper portion for support of 64 cores */
105 	u32     coredisrl;      /* lower portion for support of 64 cores */
106 	u8      res_09c[0xa4-0x9c];
107 	u32     svr;            /* System version */
108 	u8	res_0a8[0xb0-0xa8];
109 	u32	rstcr;		/* Reset control */
110 	u32	rstrqpblsr;	/* Reset request preboot loader status */
111 	u8	res_0b8[0xc0-0xb8];
112 	u32	rstrqmr1;	/* Reset request mask */
113 	u8	res_0c4[0xc8-0xc4];
114 	u32	rstrqsr1;	/* Reset request status */
115 	u8	res_0cc[0xd4-0xcc];
116 	u32	rstrqwdtmrl;	/* Reset request WDT mask */
117 	u8	res_0d8[0xdc-0xd8];
118 	u32	rstrqwdtsrl;	/* Reset request WDT status */
119 	u8	res_0e0[0xe4-0xe0];
120 	u32	brrl;		/* Boot release */
121 	u8      res_0e8[0x100-0xe8];
122 	u32     rcwsr[16];      /* Reset control word status */
123 #define RCW_SB_EN_REG_INDEX	7
124 #define RCW_SB_EN_MASK		0x00200000
125 	u8      res_140[0x200-0x140];
126 	u32     scratchrw[4];  /* Scratch Read/Write */
127 	u8      res_210[0x300-0x210];
128 	u32     scratchw1r[4];  /* Scratch Read (Write once) */
129 	u8      res_310[0x400-0x310];
130 	u32	crstsr;
131 	u8      res_404[0x550-0x404];
132 	u32	sataliodnr;
133 	u8	res_554[0x604-0x554];
134 	u32	pamubypenr;
135 	u32	dmacr1;
136 	u8      res_60c[0x740-0x60c];   /* add more registers when needed */
137 	u32     tp_ityp[64];    /* Topology Initiator Type Register */
138 	struct {
139 		u32     upper;
140 		u32     lower;
141 	} tp_cluster[1];        /* Core Cluster n Topology Register */
142 	u8	res_848[0xe60-0x848];
143 	u32	ddrclkdr;
144 	u8	res_e60[0xe68-0xe64];
145 	u32	ifcclkdr;
146 	u8	res_e68[0xe80-0xe6c];
147 	u32	sdhcpcr;
148 };
149 
150 #define SCFG_ETSECDMAMCR_LE_BD_FR	0x00000c00
151 #define SCFG_SNPCNFGCR_SEC_RD_WR	0xc0000000
152 #define SCFG_ETSECCMCR_GE2_CLK125	0x04000000
153 #define SCFG_ETSECCMCR_GE0_CLK125	0x00000000
154 #define SCFG_ETSECCMCR_GE1_CLK125	0x08000000
155 #define SCFG_PIXCLKCR_PXCKEN		0x80000000
156 #define SCFG_QSPI_CLKSEL		0xc0100000
157 #define SCFG_SNPCNFGCR_SEC_RD_WR	0xc0000000
158 #define SCFG_SNPCNFGCR_DCU_RD_WR	0x03000000
159 #define SCFG_SNPCNFGCR_SATA_RD_WR	0x00c00000
160 #define SCFG_SNPCNFGCR_USB3_RD_WR	0x00300000
161 #define SCFG_SNPCNFGCR_DBG_RD_WR	0x000c0000
162 #define SCFG_SNPCNFGCR_EDMA_SNP		0x00020000
163 #define SCFG_ENDIANCR_LE		0x80000000
164 #define SCFG_DPSLPCR_WDRR_EN		0x00000001
165 #define SCFG_PMCINTECR_LPUART		0x40000000
166 #define SCFG_PMCINTECR_FTM		0x20000000
167 #define SCFG_PMCINTECR_GPIO		0x10000000
168 #define SCFG_PMCINTECR_IRQ0		0x08000000
169 #define SCFG_PMCINTECR_IRQ1		0x04000000
170 #define SCFG_PMCINTECR_ETSECRXG0	0x00800000
171 #define SCFG_PMCINTECR_ETSECRXG1	0x00400000
172 #define SCFG_PMCINTECR_ETSECERRG0	0x00080000
173 #define SCFG_PMCINTECR_ETSECERRG1	0x00040000
174 #define SCFG_CLUSTERPMCR_WFIL2EN	0x80000000
175 
176 #define SCFG_BASE			0x01570000
177 #define SCFG_USB3PRM1CR			0x070
178 #define SCFG_USB_TXVREFTUNE		0x9
179 #define SCFG_USB_SQRXTUNE_MASK		0x7
180 #define SCFG_USB3PRM2CR			0x074
181 #define SCFG_USB_PCSTXSWINGFULL_MASK	0x0000FE00
182 #define SCFG_USB_PCSTXSWINGFULL_VAL		0x00008E00
183 
184 #define USB_PHY_BASE			0x08510000
185 #define USB_PHY_RX_OVRD_IN_HI	0x200c
186 #define USB_PHY_RX_EQ_VAL_1		0x0000
187 #define USB_PHY_RX_EQ_VAL_2		0x8000
188 #define USB_PHY_RX_EQ_VAL_3		0x8004
189 #define USB_PHY_RX_EQ_VAL_4		0x800C
190 
191 /* Supplemental Configuration Unit */
192 struct ccsr_scfg {
193 	u32 dpslpcr;
194 	u32 resv0[2];
195 	u32 etsecclkdpslpcr;
196 	u32 resv1[5];
197 	u32 fuseovrdcr;
198 	u32 pixclkcr;
199 	u32 resv2[5];
200 	u32 spimsicr;
201 	u32 resv3[6];
202 	u32 pex1pmwrcr;
203 	u32 pex1pmrdsr;
204 	u32 resv4[3];
205 	u32 usb3prm1cr;
206 	u32 usb4prm2cr;
207 	u32 pex1rdmsgpldlsbsr;
208 	u32 pex1rdmsgpldmsbsr;
209 	u32 pex2rdmsgpldlsbsr;
210 	u32 pex2rdmsgpldmsbsr;
211 	u32 pex1rdmmsgrqsr;
212 	u32 pex2rdmmsgrqsr;
213 	u32 spimsiclrcr;
214 	u32 pexmscportsr[2];
215 	u32 pex2pmwrcr;
216 	u32 resv5[24];
217 	u32 mac1_streamid;
218 	u32 mac2_streamid;
219 	u32 mac3_streamid;
220 	u32 pex1_streamid;
221 	u32 pex2_streamid;
222 	u32 dma_streamid;
223 	u32 sata_streamid;
224 	u32 usb3_streamid;
225 	u32 qe_streamid;
226 	u32 sdhc_streamid;
227 	u32 adma_streamid;
228 	u32 letechsftrstcr;
229 	u32 core0_sft_rst;
230 	u32 core1_sft_rst;
231 	u32 resv6[1];
232 	u32 usb_hi_addr;
233 	u32 etsecclkadjcr;
234 	u32 sai_clk;
235 	u32 resv7[1];
236 	u32 dcu_streamid;
237 	u32 usb2_streamid;
238 	u32 ftm_reset;
239 	u32 altcbar;
240 	u32 qspi_cfg;
241 	u32 pmcintecr;
242 	u32 pmcintlecr;
243 	u32 pmcintsr;
244 	u32 qos1;
245 	u32 qos2;
246 	u32 qos3;
247 	u32 cci_cfg;
248 	u32 endiancr;
249 	u32 etsecdmamcr;
250 	u32 usb3prm3cr;
251 	u32 resv9[1];
252 	u32 debug_streamid;
253 	u32 resv10[5];
254 	u32 snpcnfgcr;
255 	u32 hrstcr;
256 	u32 intpcr;
257 	u32 resv12[20];
258 	u32 scfgrevcr;
259 	u32 coresrencr;
260 	u32 pex2pmrdsr;
261 	u32 eddrtqcfg;
262 	u32 ddrc2cr;
263 	u32 ddrc3cr;
264 	u32 ddrc4cr;
265 	u32 ddrgcr;
266 	u32 resv13[120];
267 	u32 qeioclkcr;
268 	u32 etsecmcr;
269 	u32 sdhciovserlcr;
270 	u32 resv14[61];
271 	u32 sparecr[8];
272 	u32 resv15[248];
273 	u32 core0sftrstsr;
274 	u32 clusterpmcr;
275 };
276 
277 /* Clocking */
278 struct ccsr_clk {
279 	struct {
280 		u32 clkcncsr;	/* core cluster n clock control status */
281 		u8  res_004[0x1c];
282 	} clkcsr[2];
283 	u8	res_040[0x7c0]; /* 0x100 */
284 	struct {
285 		u32 pllcngsr;
286 		u8 res_804[0x1c];
287 	} pllcgsr[2];
288 	u8	res_840[0x1c0];
289 	u32	clkpcsr;	/* 0xa00 Platform clock domain control/status */
290 	u8	res_a04[0x1fc];
291 	u32	pllpgsr;	/* 0xc00 Platform PLL General Status */
292 	u8	res_c04[0x1c];
293 	u32	plldgsr;	/* 0xc20 DDR PLL General Status */
294 	u8	res_c24[0x3dc];
295 };
296 
297 /* System Counter */
298 struct sctr_regs {
299 	u32 cntcr;
300 	u32 cntsr;
301 	u32 cntcv1;
302 	u32 cntcv2;
303 	u32 resv1[4];
304 	u32 cntfid0;
305 	u32 cntfid1;
306 	u32 resv2[1002];
307 	u32 counterid[12];
308 };
309 
310 #define MAX_SERDES			1
311 #define SRDS_MAX_LANES			4
312 #define SRDS_MAX_BANK			2
313 
314 #define SRDS_RSTCTL_RST			0x80000000
315 #define SRDS_RSTCTL_RSTDONE		0x40000000
316 #define SRDS_RSTCTL_RSTERR		0x20000000
317 #define SRDS_RSTCTL_SWRST		0x10000000
318 #define SRDS_RSTCTL_SDEN		0x00000020
319 #define SRDS_RSTCTL_SDRST_B		0x00000040
320 #define SRDS_RSTCTL_PLLRST_B		0x00000080
321 #define SRDS_PLLCR0_POFF		0x80000000
322 #define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
323 #define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
324 #define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
325 #define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
326 #define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
327 #define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
328 #define SRDS_PLLCR0_RFCK_SEL_122_88	0x50000000
329 #define SRDS_PLLCR0_PLL_LCK		0x00800000
330 #define SRDS_PLLCR0_FRATE_SEL_MASK	0x000f0000
331 #define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
332 #define SRDS_PLLCR0_FRATE_SEL_3_75	0x00050000
333 #define SRDS_PLLCR0_FRATE_SEL_5_15	0x00060000
334 #define SRDS_PLLCR0_FRATE_SEL_4		0x00070000
335 #define SRDS_PLLCR0_FRATE_SEL_3_12	0x00090000
336 #define SRDS_PLLCR0_FRATE_SEL_3		0x000a0000
337 #define SRDS_PLLCR1_PLL_BWSEL		0x08000000
338 
339 struct ccsr_serdes {
340 	struct {
341 		u32	rstctl;	/* Reset Control Register */
342 
343 		u32	pllcr0; /* PLL Control Register 0 */
344 
345 		u32	pllcr1; /* PLL Control Register 1 */
346 		u32	res_0c;	/* 0x00c */
347 		u32	pllcr3;
348 		u32	pllcr4;
349 		u8	res_18[0x20-0x18];
350 	} bank[2];
351 	u8	res_40[0x90-0x40];
352 	u32	srdstcalcr;	/* 0x90 TX Calibration Control */
353 	u8	res_94[0xa0-0x94];
354 	u32	srdsrcalcr;	/* 0xa0 RX Calibration Control */
355 	u8	res_a4[0xb0-0xa4];
356 	u32	srdsgr0;	/* 0xb0 General Register 0 */
357 	u8	res_b4[0xe0-0xb4];
358 	u32	srdspccr0;	/* 0xe0 Protocol Converter Config 0 */
359 	u32	srdspccr1;	/* 0xe4 Protocol Converter Config 1 */
360 	u32	srdspccr2;	/* 0xe8 Protocol Converter Config 2 */
361 	u32	srdspccr3;	/* 0xec Protocol Converter Config 3 */
362 	u32	srdspccr4;	/* 0xf0 Protocol Converter Config 4 */
363 	u8	res_f4[0x100-0xf4];
364 	struct {
365 		u32	lnpssr;	/* 0x100, 0x120, ..., 0x1e0 */
366 		u8	res_104[0x120-0x104];
367 	} srdslnpssr[4];
368 	u8	res_180[0x300-0x180];
369 	u32	srdspexeqcr;
370 	u32	srdspexeqpcr[11];
371 	u8	res_330[0x400-0x330];
372 	u32	srdspexapcr;
373 	u8	res_404[0x440-0x404];
374 	u32	srdspexbpcr;
375 	u8	res_444[0x800-0x444];
376 	struct {
377 		u32	gcr0;	/* 0x800 General Control Register 0 */
378 		u32	gcr1;	/* 0x804 General Control Register 1 */
379 		u32	gcr2;	/* 0x808 General Control Register 2 */
380 		u32	sscr0;
381 		u32	recr0;	/* 0x810 Receive Equalization Control */
382 		u32	recr1;
383 		u32	tecr0;	/* 0x818 Transmit Equalization Control */
384 		u32	sscr1;
385 		u32	ttlcr0;	/* 0x820 Transition Tracking Loop Ctrl 0 */
386 		u8	res_824[0x83c-0x824];
387 		u32	tcsr3;
388 	} lane[4];	/* Lane A, B, C, D, E, F, G, H */
389 	u8	res_a00[0x1000-0xa00];	/* from 0xa00 to 0xfff */
390 };
391 
392 
393 
394 /* AHCI (sata) register map */
395 struct ccsr_ahci {
396 	u32 res1[0xa4/4];	/* 0x0 - 0xa4 */
397 	u32 pcfg;	/* port config */
398 	u32 ppcfg;	/* port phy1 config */
399 	u32 pp2c;	/* port phy2 config */
400 	u32 pp3c;	/* port phy3 config */
401 	u32 pp4c;	/* port phy4 config */
402 	u32 pp5c;	/* port phy5 config */
403 	u32 paxic;	/* port AXI config */
404 	u32 axicc;	/* AXI cache control */
405 	u32 axipc;	/* AXI PROT control */
406 	u32 ptc;	/* port Trans Config */
407 	u32 pts;	/* port Trans Status */
408 	u32 plc;	/* port link config */
409 	u32 plc1;	/* port link config1 */
410 	u32 plc2;	/* port link config2 */
411 	u32 pls;	/* port link status */
412 	u32 pls1;	/* port link status1 */
413 	u32 pcmdc;	/* port CMD config */
414 	u32 ppcs;	/* port phy control status */
415 	u32 pberr;	/* port 0/1 BIST error */
416 	u32 cmds;	/* port 0/1 CMD status error */
417 };
418 
419 #define RCPM_POWMGTCSR			0x130
420 #define RCPM_POWMGTCSR_SERDES_PW	0x80000000
421 #define RCPM_POWMGTCSR_LPM20_REQ	0x00100000
422 #define RCPM_POWMGTCSR_LPM20_ST		0x00000200
423 #define RCPM_POWMGTCSR_P_LPM20_ST	0x00000100
424 #define RCPM_IPPDEXPCR0			0x140
425 #define RCPM_IPPDEXPCR0_ETSEC		0x80000000
426 #define RCPM_IPPDEXPCR0_GPIO		0x00000040
427 #define RCPM_IPPDEXPCR1			0x144
428 #define RCPM_IPPDEXPCR1_LPUART		0x40000000
429 #define RCPM_IPPDEXPCR1_FLEXTIMER	0x20000000
430 #define RCPM_IPPDEXPCR1_OCRAM1		0x10000000
431 #define RCPM_NFIQOUTR			0x15c
432 #define RCPM_NIRQOUTR			0x16c
433 #define RCPM_DSIMSKR			0x18c
434 #define RCPM_CLPCL10SETR		0x1c4
435 #define RCPM_CLPCL10SETR_C0		0x00000001
436 
437 struct ccsr_rcpm {
438 	u8 rev1[0x4c];
439 	u32 twaitsr;
440 	u8 rev2[0xe0];
441 	u32 powmgtcsr;
442 	u8 rev3[0xc];
443 	u32 ippdexpcr0;
444 	u32 ippdexpcr1;
445 	u8 rev4[0x14];
446 	u32 nfiqoutr;
447 	u8 rev5[0xc];
448 	u32 nirqoutr;
449 	u8 rev6[0x1c];
450 	u32 dsimskr;
451 	u8 rev7[0x34];
452 	u32 clpcl10setr;
453 };
454 
455 uint get_svr(void);
456 
457 #endif	/* __ASM_ARCH_LS102XA_IMMAP_H_ */
458