Searched refs:ahb_reset1_cfg (Results 1 – 8 of 8) sorted by relevance
| /external/u-boot/drivers/video/sunxi/ |
| D | sunxi_dw_hdmi.c | 254 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0); in sunxi_dw_hdmi_lcdc_init()
264 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1); in sunxi_dw_hdmi_lcdc_init()
341 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); in sunxi_dw_hdmi_probe()
342 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2); in sunxi_dw_hdmi_probe()
|
| D | sunxi_display.c | 106 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); in sunxi_hdmi_hpd_detect()
135 clrbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI); in sunxi_hdmi_shutdown()
446 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE_BE0); in sunxi_composer_init()
528 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0); in sunxi_lcdc_init()
861 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_SAT);
863 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DRC0);
|
| D | sunxi_lcd.c | 49 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0); in sunxi_lcd_enable()
|
| D | sunxi_de2.c | 54 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE); in sunxi_de2_composer_init()
|
| /external/u-boot/arch/arm/mach-sunxi/ |
| D | clock_sun9i.c | 61 setbits_le32(&ccm->ahb_reset1_cfg, (1 << 24)); in clock_init_safe()
|
| /external/u-boot/arch/arm/include/asm/arch-sunxi/ |
| D | clock_sun9i.h | 91 u32 ahb_reset1_cfg; /* 0x5a4 AHB1 Software Reset Register */ member
|
| D | clock_sun8i_a83t.h | 121 u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */ member
|
| D | clock_sun6i.h | 151 u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */ member
|