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Searched refs:alu (Results 1 – 25 of 81) sorted by relevance

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/external/mesa3d/src/gallium/drivers/r600/
Dr700_asm.c37 int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu *alu, unsigned id) in r700_bytecode_alu_build() argument
39 bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) | in r700_bytecode_alu_build()
40 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) | in r700_bytecode_alu_build()
41 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) | in r700_bytecode_alu_build()
42 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) | in r700_bytecode_alu_build()
43 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) | in r700_bytecode_alu_build()
44 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) | in r700_bytecode_alu_build()
45 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) | in r700_bytecode_alu_build()
46 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) | in r700_bytecode_alu_build()
47 S_SQ_ALU_WORD0_PRED_SEL(alu->pred_sel) | in r700_bytecode_alu_build()
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Dr600_shader.c500 struct r600_bytecode_alu alu; in evergreen_interp_alu() local
509 memset(&alu, 0, sizeof(struct r600_bytecode_alu)); in evergreen_interp_alu()
512 alu.op = ALU_OP2_INTERP_ZW; in evergreen_interp_alu()
514 alu.op = ALU_OP2_INTERP_XY; in evergreen_interp_alu()
517 alu.dst.sel = ctx->shader->input[input].gpr; in evergreen_interp_alu()
518 alu.dst.write = 1; in evergreen_interp_alu()
521 alu.dst.chan = i % 4; in evergreen_interp_alu()
523 alu.src[0].sel = gpr; in evergreen_interp_alu()
524 alu.src[0].chan = (base_chan - (i % 2)); in evergreen_interp_alu()
526 alu.src[1].sel = V_SQ_ALU_SRC_PARAM_BASE + ctx->shader->input[input].lds_pos; in evergreen_interp_alu()
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Deg_asm.c177 struct r600_bytecode_alu alu; in egcm_load_index_reg() local
187 memset(&alu, 0, sizeof(alu)); in egcm_load_index_reg()
188 alu.op = ALU_OP1_MOVA_INT; in egcm_load_index_reg()
189 alu.src[0].sel = bc->index_reg[id]; in egcm_load_index_reg()
190 alu.src[0].chan = 0; in egcm_load_index_reg()
192 alu.dst.sel = id == 0 ? CM_V_SQ_MOVA_DST_CF_IDX0 : CM_V_SQ_MOVA_DST_CF_IDX1; in egcm_load_index_reg()
194 alu.last = 1; in egcm_load_index_reg()
195 r = r600_bytecode_add_alu(bc, &alu); in egcm_load_index_reg()
202 memset(&alu, 0, sizeof(alu)); in egcm_load_index_reg()
203 alu.op = id == 0 ? ALU_OP0_SET_CF_IDX0 : ALU_OP0_SET_CF_IDX1; in egcm_load_index_reg()
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Dr600_asm.c41 static inline bool alu_writes(struct r600_bytecode_alu *alu) in alu_writes() argument
43 return alu->dst.write || alu->is_op3; in alu_writes()
46 static inline unsigned int r600_bytecode_get_num_operands(const struct r600_bytecode_alu *alu) in r600_bytecode_get_num_operands() argument
48 return r600_isa_alu(alu->op)->src_count; in r600_bytecode_get_num_operands()
58 LIST_INITHEAD(&cf->alu); in r600_bytecode_cf()
67 struct r600_bytecode_alu *alu = CALLOC_STRUCT(r600_bytecode_alu); in r600_bytecode_alu() local
69 if (!alu) in r600_bytecode_alu()
71 LIST_INITHEAD(&alu->list); in r600_bytecode_alu()
72 return alu; in r600_bytecode_alu()
235 static int is_alu_once_inst(struct r600_bytecode_alu *alu) in is_alu_once_inst() argument
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/external/mesa3d/src/compiler/nir/
Dnir_lower_to_source_mods.c45 nir_alu_instr *alu = nir_instr_as_alu(instr); in nir_lower_to_source_mods_block() local
47 for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) { in nir_lower_to_source_mods_block()
48 if (!alu->src[i].src.is_ssa) in nir_lower_to_source_mods_block()
51 if (alu->src[i].src.ssa->parent_instr->type != nir_instr_type_alu) in nir_lower_to_source_mods_block()
54 nir_alu_instr *parent = nir_instr_as_alu(alu->src[i].src.ssa->parent_instr); in nir_lower_to_source_mods_block()
59 switch (nir_alu_type_get_base_type(nir_op_infos[alu->op].input_types[i])) { in nir_lower_to_source_mods_block()
79 nir_instr_rewrite_src(instr, &alu->src[i].src, parent->src[0].src); in nir_lower_to_source_mods_block()
80 if (alu->src[i].abs) { in nir_lower_to_source_mods_block()
83 alu->src[i].negate = (alu->src[i].negate != parent->src[0].negate); in nir_lower_to_source_mods_block()
84 alu->src[i].abs |= parent->src[0].abs; in nir_lower_to_source_mods_block()
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Dnir_opt_undef.c78 opt_undef_vecN(nir_builder *b, nir_alu_instr *alu) in opt_undef_vecN() argument
80 if (alu->op != nir_op_vec2 && in opt_undef_vecN()
81 alu->op != nir_op_vec3 && in opt_undef_vecN()
82 alu->op != nir_op_vec4 && in opt_undef_vecN()
83 alu->op != nir_op_fmov && in opt_undef_vecN()
84 alu->op != nir_op_imov) in opt_undef_vecN()
87 assert(alu->dest.dest.is_ssa); in opt_undef_vecN()
89 for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) { in opt_undef_vecN()
90 if (!alu->src[i].src.is_ssa || in opt_undef_vecN()
91 alu->src[i].src.ssa->parent_instr->type != nir_instr_type_ssa_undef) in opt_undef_vecN()
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Dnir_lower_regs_to_ssa.c107 rewrite_alu_instr(nir_alu_instr *alu, struct regs_to_ssa_state *state) in rewrite_alu_instr() argument
109 nir_foreach_src(&alu->instr, rewrite_src, state); in rewrite_alu_instr()
111 if (alu->dest.dest.is_ssa) in rewrite_alu_instr()
114 nir_register *reg = alu->dest.dest.reg.reg; in rewrite_alu_instr()
119 unsigned write_mask = alu->dest.write_mask; in rewrite_alu_instr()
124 rewrite_dest(&alu->dest.dest, state); in rewrite_alu_instr()
135 if (nir_op_infos[alu->op].output_size == 0) { in rewrite_alu_instr()
148 for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) { in rewrite_alu_instr()
149 if (nir_op_infos[alu->op].input_sizes[i] != 0) in rewrite_alu_instr()
167 alu->src[i].swizzle[ssa_index++] = alu->src[i].swizzle[index]; in rewrite_alu_instr()
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Dnir_loop_analyze.c166 nir_alu_instr *alu = nir_instr_as_alu(def->parent_instr); in mark_invariant() local
168 for (unsigned i = 0; i < nir_op_infos[alu->op].num_inputs; i++) { in mark_invariant()
169 if (!mark_invariant(alu->src[i].src.ssa, state)) { in mark_invariant()
243 nir_alu_instr *alu = nir_instr_as_alu(src_var->def->parent_instr); in compute_induction_information() local
245 if (nir_op_infos[alu->op].num_inputs == 2) { in compute_induction_information()
247 biv->alu_op = alu->op; in compute_induction_information()
251 if (alu->src[i].src.ssa->parent_instr->type == nir_instr_type_load_const && in compute_induction_information()
252 alu->src[1-i].src.ssa == &phi->dest.ssa) in compute_induction_information()
253 biv->invariant = get_loop_var(alu->src[i].src.ssa, state); in compute_induction_information()
455 nir_alu_instr *alu = nir_instr_as_alu(alu_def->def->parent_instr); in calculate_iterations() local
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Dnir_lower_idiv.c40 convert_instr(nir_builder *bld, nir_alu_instr *alu) in convert_instr() argument
43 nir_op op = alu->op; in convert_instr()
53 bld->cursor = nir_before_instr(&alu->instr); in convert_instr()
55 numer = nir_ssa_for_alu_src(bld, alu, 0); in convert_instr()
56 denom = nir_ssa_for_alu_src(bld, alu, 1); in convert_instr()
115 assert(alu->dest.dest.is_ssa); in convert_instr()
116 nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa, nir_src_for_ssa(q)); in convert_instr()
/external/mesa3d/src/broadcom/qpu/
Dqpu_pack.c729 instr->alu.add.op = desc->op; in v3d_qpu_add_unpack()
735 if (instr->alu.add.op == V3D_QPU_A_FMIN) in v3d_qpu_add_unpack()
736 instr->alu.add.op = V3D_QPU_A_FMAX; in v3d_qpu_add_unpack()
737 if (instr->alu.add.op == V3D_QPU_A_FADD) in v3d_qpu_add_unpack()
738 instr->alu.add.op = V3D_QPU_A_FADDNF; in v3d_qpu_add_unpack()
744 switch (instr->alu.add.op) { in v3d_qpu_add_unpack()
750 instr->alu.add.op = V3D_QPU_A_STVPMV; in v3d_qpu_add_unpack()
753 instr->alu.add.op = V3D_QPU_A_STVPMD; in v3d_qpu_add_unpack()
756 instr->alu.add.op = V3D_QPU_A_STVPMP; in v3d_qpu_add_unpack()
766 switch (instr->alu.add.op) { in v3d_qpu_add_unpack()
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Dqpu_disasm.c104 bool has_dst = v3d_qpu_add_op_has_dst(instr->alu.add.op); in v3d_qpu_disasm_add()
105 int num_src = v3d_qpu_add_op_num_src(instr->alu.add.op); in v3d_qpu_disasm_add()
107 append(disasm, "%s", v3d_qpu_add_op_name(instr->alu.add.op)); in v3d_qpu_disasm_add()
116 v3d_qpu_disasm_waddr(disasm, instr->alu.add.waddr, in v3d_qpu_disasm_add()
117 instr->alu.add.magic_write); in v3d_qpu_disasm_add()
118 append(disasm, v3d_qpu_pack_name(instr->alu.add.output_pack)); in v3d_qpu_disasm_add()
124 v3d_qpu_disasm_raddr(disasm, instr, instr->alu.add.a); in v3d_qpu_disasm_add()
126 v3d_qpu_unpack_name(instr->alu.add.a_unpack)); in v3d_qpu_disasm_add()
131 v3d_qpu_disasm_raddr(disasm, instr, instr->alu.add.b); in v3d_qpu_disasm_add()
133 v3d_qpu_unpack_name(instr->alu.add.b_unpack)); in v3d_qpu_disasm_add()
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Dqpu_instr.c562 if (v3d_qpu_add_op_uses_vpm(inst->alu.add.op)) in v3d_qpu_uses_vpm()
565 if (inst->alu.add.magic_write && in v3d_qpu_uses_vpm()
566 v3d_qpu_magic_waddr_is_vpm(inst->alu.add.waddr)) { in v3d_qpu_uses_vpm()
570 if (inst->alu.mul.magic_write && in v3d_qpu_uses_vpm()
571 v3d_qpu_magic_waddr_is_vpm(inst->alu.mul.waddr)) { in v3d_qpu_uses_vpm()
584 if (inst->alu.add.magic_write && in v3d_qpu_writes_r3()
585 inst->alu.add.waddr == V3D_QPU_WADDR_R3) { in v3d_qpu_writes_r3()
589 if (inst->alu.mul.magic_write && in v3d_qpu_writes_r3()
590 inst->alu.mul.waddr == V3D_QPU_WADDR_R3) { in v3d_qpu_writes_r3()
611 if (inst->alu.add.magic_write && in v3d_qpu_writes_r4()
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/external/mesa3d/src/gallium/drivers/r300/compiler/
Dr300_fragprog.c136 int regc = code->alu.inst[i].rgb_addr >> (j * 6); in r300FragmentProgramDump()
137 int rega = code->alu.inst[i].alpha_addr >> (j * 6); in r300FragmentProgramDump()
139 code->alu.inst[i].r400_ext_addr); in r300FragmentProgramDump()
141 code->alu.inst[i].r400_ext_addr); in r300FragmentProgramDump()
151 (code->alu.inst[i]. in r300FragmentProgramDump()
153 (code->alu.inst[i]. in r300FragmentProgramDump()
155 (code->alu.inst[i]. in r300FragmentProgramDump()
160 code->alu.inst[i].r400_ext_addr); in r300FragmentProgramDump()
163 ((code->alu.inst[i]. in r300FragmentProgramDump()
169 (code->alu.inst[i]. in r300FragmentProgramDump()
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Dr300_fragprog_emit.c157 if (code->alu.length >= c->Base.max_alu_insts) { in emit_alu()
162 ip = code->alu.length++; in emit_alu()
164 code->alu.inst[ip].rgb_inst = translate_rgb_opcode(c, inst->RGB.Opcode); in emit_alu()
165 code->alu.inst[ip].alpha_inst = translate_alpha_opcode(c, inst->Alpha.Opcode); in emit_alu()
172 code->alu.inst[ip].r400_ext_addr |= R400_ADDR_EXT_RGB_MSB_BIT(j); in emit_alu()
174 code->alu.inst[ip].rgb_addr |= src << (6*j); in emit_alu()
179 code->alu.inst[ip].r400_ext_addr |= R400_ADDR_EXT_A_MSB_BIT(j); in emit_alu()
181 code->alu.inst[ip].alpha_addr |= src << (6*j); in emit_alu()
186 code->alu.inst[ip].rgb_inst |= arg << (7*j); in emit_alu()
191 code->alu.inst[ip].alpha_inst |= arg << (7*j); in emit_alu()
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/external/mesa3d/src/gallium/drivers/freedreno/a2xx/
Ddisasm-a2xx.c217 instr_alu_t *alu = (instr_alu_t *)dwords; in disasm_alu() local
227 printf("%s", vector_instructions[alu->vector_opc].name); in disasm_alu()
229 if (alu->pred_select & 0x2) { in disasm_alu()
233 printf((alu->pred_select & 0x1) ? "EQ" : "NE"); in disasm_alu()
238 print_dstreg(alu->vector_dest, alu->vector_write_mask, alu->export_data); in disasm_alu()
240 if (vector_instructions[alu->vector_opc].num_srcs == 3) { in disasm_alu()
241 print_srcreg(alu->src3_reg, alu->src3_sel, alu->src3_swiz, in disasm_alu()
242 alu->src3_reg_negate, alu->src3_reg_abs); in disasm_alu()
245 print_srcreg(alu->src1_reg, alu->src1_sel, alu->src1_swiz, in disasm_alu()
246 alu->src1_reg_negate, alu->src1_reg_abs); in disasm_alu()
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Dfd2_compiler.c316 add_dst_reg(struct fd2_compile_context *ctx, struct ir2_instruction *alu, in add_dst_reg() argument
354 return ir2_reg_create(alu, num, swiz, flags); in add_dst_reg()
358 add_src_reg(struct fd2_compile_context *ctx, struct ir2_instruction *alu, in add_src_reg() argument
407 alu->sync = true; in add_src_reg()
411 return ir2_reg_create(alu, num, swiz, flags); in add_src_reg()
415 add_vector_clamp(struct tgsi_full_instruction *inst, struct ir2_instruction *alu) in add_vector_clamp() argument
418 alu->alu.vector_clamp = true; in add_vector_clamp()
423 add_scalar_clamp(struct tgsi_full_instruction *inst, struct ir2_instruction *alu) in add_scalar_clamp() argument
426 alu->alu.scalar_clamp = true; in add_scalar_clamp()
432 struct tgsi_full_instruction *inst, struct ir2_instruction *alu) in add_regs_vector_1() argument
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Dir-a2xx.c366 instr_alu_t *alu = (instr_alu_t *)dwords; in instr_emit_alu() local
372 memset(alu, 0, sizeof(*alu)); in instr_emit_alu()
375 switch (instr->alu.vector_opc) { in instr_emit_alu()
406 if (instr->alu.vector_opc == (instr_vector_opc_t)~0) { in instr_emit_alu()
407 alu->vector_opc = MAXv; in instr_emit_alu()
408 alu->vector_write_mask = 0; in instr_emit_alu()
410 alu->vector_opc = instr->alu.vector_opc; in instr_emit_alu()
411 alu->vector_write_mask = reg_alu_dst_swiz(dst_reg); in instr_emit_alu()
414 alu->vector_dest = dst_reg->num; in instr_emit_alu()
415 alu->export_data = !!(dst_reg->flags & IR2_REG_EXPORT); in instr_emit_alu()
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/external/mesa3d/src/broadcom/compiler/
Dqpu_validate.c88 if (inst->alu.add.op != V3D_QPU_A_NOP && in qpu_magic_waddr_matches()
89 inst->alu.add.magic_write && in qpu_magic_waddr_matches()
90 predicate(inst->alu.add.waddr)) in qpu_magic_waddr_matches()
93 if (inst->alu.mul.op != V3D_QPU_M_NOP && in qpu_magic_waddr_matches()
94 inst->alu.mul.magic_write && in qpu_magic_waddr_matches()
95 predicate(inst->alu.mul.waddr)) in qpu_magic_waddr_matches()
125 if (inst->alu.add.op != V3D_QPU_A_NOP) { in qpu_validate_inst()
126 if (inst->alu.add.magic_write) { in qpu_validate_inst()
127 if (v3d_qpu_magic_waddr_is_tmu(inst->alu.add.waddr)) in qpu_validate_inst()
129 if (v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr)) in qpu_validate_inst()
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Dqpu_schedule.c160 if (inst->alu.add.magic_write && in qpu_inst_is_tlb()
161 (inst->alu.add.waddr == V3D_QPU_WADDR_TLB || in qpu_inst_is_tlb()
162 inst->alu.add.waddr == V3D_QPU_WADDR_TLBU)) in qpu_inst_is_tlb()
165 if (inst->alu.mul.magic_write && in qpu_inst_is_tlb()
166 (inst->alu.mul.waddr == V3D_QPU_WADDR_TLB || in qpu_inst_is_tlb()
167 inst->alu.mul.waddr == V3D_QPU_WADDR_TLBU)) in qpu_inst_is_tlb()
301 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 0) in calculate_deps()
302 process_mux_deps(state, n, inst->alu.add.a); in calculate_deps()
303 if (v3d_qpu_add_op_num_src(inst->alu.add.op) > 1) in calculate_deps()
304 process_mux_deps(state, n, inst->alu.add.b); in calculate_deps()
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Dvir_to_qpu.c59 .alu = { in v3d_qpu_nop()
119 if (instr->alu.add.a != V3D_QPU_MUX_A && in set_src()
120 instr->alu.add.b != V3D_QPU_MUX_A && in set_src()
121 instr->alu.mul.a != V3D_QPU_MUX_A && in set_src()
122 instr->alu.mul.b != V3D_QPU_MUX_A) { in set_src()
129 assert(!(instr->alu.add.a == V3D_QPU_MUX_B && in set_src()
130 instr->alu.add.b == V3D_QPU_MUX_B && in set_src()
131 instr->alu.mul.a == V3D_QPU_MUX_B && in set_src()
132 instr->alu.mul.b == V3D_QPU_MUX_B) || in set_src()
262 assert(qinst->qpu.alu.add.op == V3D_QPU_A_NOP); in v3d_generate_code_block()
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Dvir_opt_copy_propagate.c44 (inst->qpu.alu.mul.op != V3D_QPU_M_FMOV && in is_copy_mov()
45 inst->qpu.alu.mul.op != V3D_QPU_M_MOV)) { in is_copy_mov()
57 if (inst->qpu.alu.add.output_pack != V3D_QPU_PACK_NONE || in is_copy_mov()
58 inst->qpu.alu.mul.output_pack != V3D_QPU_PACK_NONE) { in is_copy_mov()
109 return inst->qpu.alu.add.a_unpack != V3D_QPU_UNPACK_NONE; in vir_has_unpack()
111 return inst->qpu.alu.add.b_unpack != V3D_QPU_UNPACK_NONE; in vir_has_unpack()
114 return inst->qpu.alu.mul.a_unpack != V3D_QPU_UNPACK_NONE; in vir_has_unpack()
116 return inst->qpu.alu.mul.b_unpack != V3D_QPU_UNPACK_NONE; in vir_has_unpack()
171 enum v3d_qpu_input_unpack unpack = mov->qpu.alu.mul.a_unpack; in try_copy_prop()
/external/mesa3d/src/intel/compiler/
Dbrw_nir_opt_peephole_ffma.c81 nir_alu_instr *alu = nir_instr_as_alu(instr); in get_mul_for_src() local
90 if (alu->exact) in get_mul_for_src()
93 switch (alu->op) { in get_mul_for_src()
96 alu = get_mul_for_src(&alu->src[0], num_components, swizzle, negate, abs); in get_mul_for_src()
100 alu = get_mul_for_src(&alu->src[0], num_components, swizzle, negate, abs); in get_mul_for_src()
105 alu = get_mul_for_src(&alu->src[0], num_components, swizzle, negate, abs); in get_mul_for_src()
115 if (!are_all_uses_fadd(&alu->dest.dest.ssa)) in get_mul_for_src()
123 if (!alu) in get_mul_for_src()
139 return alu; in get_mul_for_src()
Dbrw_nir_analyze_boolean_resolves.c110 nir_alu_instr *alu = nir_instr_as_alu(instr); in analyze_boolean_resolves_block() local
111 switch (alu->op) { in analyze_boolean_resolves_block()
137 resolve_status = get_resolve_status_for_src(&alu->src[0].src); in analyze_boolean_resolves_block()
143 uint8_t src0_status = get_resolve_status_for_src(&alu->src[0].src); in analyze_boolean_resolves_block()
144 uint8_t src1_status = get_resolve_status_for_src(&alu->src[1].src); in analyze_boolean_resolves_block()
168 if (nir_alu_type_get_base_type(nir_op_infos[alu->op].output_type) == nir_type_bool) { in analyze_boolean_resolves_block()
189 if (!alu->dest.dest.is_ssa && in analyze_boolean_resolves_block()
/external/mesa3d/src/gallium/drivers/r600/sb/
Dsb_sched.cpp868 alu.reset(); in load_index_register()
872 alu_group_tracker &rt = alu.grp(); in load_index_register()
881 if (!alu.check_clause_limits()) { in load_index_register()
884 alu.emit_group(); in load_index_register()
887 alu_group_tracker &rt = alu.grp(); in load_index_register()
888 alu_node *a = alu.create_ar_load(v, ar_idx == V_SQ_CF_INDEX_1 ? SEL_Z : SEL_Y); in load_index_register()
898 if (!alu.check_clause_limits()) { in load_index_register()
902 alu.emit_group(); in load_index_register()
903 alu.emit_clause(cur_bb); in load_index_register()
954 alu.reset(); in process_alu()
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/external/mesa3d/src/broadcom/qpu/tests/
Dqpu_disasm.c135 switch (instr.alu.add.op) { in main()
143 swap_mux(&instr.alu.add.a, in main()
144 &instr.alu.add.b); in main()
145 swap_pack(&instr.alu.add.a_unpack, in main()
146 &instr.alu.add.b_unpack); in main()

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