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/external/python/cpython3/Lib/test/decimaltestdata/
DdqAnd.decTest9 -- These testcases are experimental ('beta' versions), and they --
15 -- Please send comments, suggestions, and corrections to the author: --
30 dqand001 and 0 0 -> 0
31 dqand002 and 0 1 -> 0
32 dqand003 and 1 0 -> 0
33 dqand004 and 1 1 -> 1
34 dqand005 and 1100 1010 -> 1000
35 -- and at msd and msd-1
37 dqand006 and 0000000000000000000000000000000000 0000000000000000000000000000000000 -> …
38 dqand007 and 0000000000000000000000000000000000 1000000000000000000000000000000000 -> …
[all …]
DddAnd.decTest9 -- These testcases are experimental ('beta' versions), and they --
15 -- Please send comments, suggestions, and corrections to the author: --
30 ddand001 and 0 0 -> 0
31 ddand002 and 0 1 -> 0
32 ddand003 and 1 0 -> 0
33 ddand004 and 1 1 -> 1
34 ddand005 and 1100 1010 -> 1000
35 -- and at msd and msd-1
37 ddand006 and 0000000000000000 0000000000000000 -> 0
38 ddand007 and 0000000000000000 1000000000000000 -> 0
[all …]
Dand.decTest2 -- and.decTest -- digitwise logical AND --
9 -- These testcases are experimental ('beta' versions), and they --
15 -- Please send comments, suggestions, and corrections to the author: --
29 andx001 and 0 0 -> 0
30 andx002 and 0 1 -> 0
31 andx003 and 1 0 -> 0
32 andx004 and 1 1 -> 1
33 andx005 and 1100 1010 -> 1000
34 andx006 and 1111 10 -> 10
35 andx007 and 1111 1010 -> 1010
[all …]
/external/python/cpython2/Lib/test/decimaltestdata/
DdqAnd.decTest9 -- These testcases are experimental ('beta' versions), and they --
15 -- Please send comments, suggestions, and corrections to the author: --
30 dqand001 and 0 0 -> 0
31 dqand002 and 0 1 -> 0
32 dqand003 and 1 0 -> 0
33 dqand004 and 1 1 -> 1
34 dqand005 and 1100 1010 -> 1000
35 -- and at msd and msd-1
37 dqand006 and 0000000000000000000000000000000000 0000000000000000000000000000000000 -> …
38 dqand007 and 0000000000000000000000000000000000 1000000000000000000000000000000000 -> …
[all …]
DddAnd.decTest9 -- These testcases are experimental ('beta' versions), and they --
15 -- Please send comments, suggestions, and corrections to the author: --
30 ddand001 and 0 0 -> 0
31 ddand002 and 0 1 -> 0
32 ddand003 and 1 0 -> 0
33 ddand004 and 1 1 -> 1
34 ddand005 and 1100 1010 -> 1000
35 -- and at msd and msd-1
37 ddand006 and 0000000000000000 0000000000000000 -> 0
38 ddand007 and 0000000000000000 1000000000000000 -> 0
[all …]
Dand.decTest2 -- and.decTest -- digitwise logical AND --
9 -- These testcases are experimental ('beta' versions), and they --
15 -- Please send comments, suggestions, and corrections to the author: --
29 andx001 and 0 0 -> 0
30 andx002 and 0 1 -> 0
31 andx003 and 1 0 -> 0
32 andx004 and 1 1 -> 1
33 andx005 and 1100 1010 -> 1000
34 andx006 and 1111 10 -> 10
35 andx007 and 1111 1010 -> 1010
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/CorrelatedValuePropagation/
Dcrash.ll15 %and.us.us = and i16 %conv6.us.us, %and.us.us
66 %a1 = and i1 %a0, %a0
67 %a2 = and i1 %a1, %a1
68 %a3 = and i1 %a2, %a2
69 %a4 = and i1 %a3, %a3
70 %a5 = and i1 %a4, %a4
71 %a6 = and i1 %a5, %a5
72 %a7 = and i1 %a6, %a6
73 %a8 = and i1 %a7, %a7
74 %a9 = and i1 %a8, %a8
[all …]
/external/v8/
DChangeLog3 Performance and stability improvements on all platforms.
8 Performance and stability improvements on all platforms.
13 Performance and stability improvements on all platforms.
18 Performance and stability improvements on all platforms.
23 Performance and stability improvements on all platforms.
28 Performance and stability improvements on all platforms.
33 Performance and stability improvements on all platforms.
38 Performance and stability improvements on all platforms.
43 Performance and stability improvements on all platforms.
48 Performance and stability improvements on all platforms.
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopPredication/
Dvisited.ll16 ; CHECK-NEXT: [[wide_cond:[^ ]+]] = and i1 [[first_iteration_check]], [[limit_check]]
23 ; CHECK: [[guard_cond:[^ ]+]] = and i1 %unrelated.cond, [[wide_cond]]
29 %guard.cond.2 = and i1 %within.bounds, %unrelated.cond
30 %guard.cond.3 = and i1 %guard.cond.2, %unrelated.cond
31 %guard.cond.4 = and i1 %guard.cond.3, %guard.cond.2
32 %guard.cond.5 = and i1 %guard.cond.4, %guard.cond.3
33 %guard.cond.6 = and i1 %guard.cond.5, %guard.cond.4
34 %guard.cond.7 = and i1 %guard.cond.6, %guard.cond.5
35 %guard.cond.8 = and i1 %guard.cond.7, %guard.cond.6
36 %guard.cond.9 = and i1 %guard.cond.8, %guard.cond.7
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/CellSPU/
Dselect_bits.ll11 ; (or (and rC, rB), (and (not rC), rA))
13 %C = and <2 x i64> %rC, %rB
15 %B = and <2 x i64> %A, %rA
20 ; (or (and rB, rC), (and (not rC), rA))
22 %C = and <2 x i64> %rB, %rC
24 %B = and <2 x i64> %A, %rA
29 ; (or (and (not rC), rA), (and rB, rC))
32 %B = and <2 x i64> %A, %rA
33 %C = and <2 x i64> %rB, %rC
38 ; (or (and (not rC), rA), (and rC, rB))
[all …]
/external/llvm/test/CodeGen/SystemZ/
Drisbg-01.ll12 %and = and i32 %shr, 1
13 ret i32 %and
16 ; ...and again with i64.
22 %and = and i64 %shr, 1
23 ret i64 %and
32 %and = and i32 %shr, 12
33 ret i32 %and
36 ; ...and again with i64.
42 %and = and i64 %shr, 12
43 ret i64 %and
[all …]
Dand-02.ll10 %and = and i32 %a, 1
11 ret i32 %and
19 %and = and i32 %b, 1
20 ret i32 %and
28 %and = and i32 %b, 4
29 ret i32 %and
37 %and = and i32 %a, 5
38 ret i32 %and
46 %and = and i32 %b, 5
47 ret i32 %and
[all …]
Dand-04.ll10 %and = and i64 %a, 1
11 ret i64 %and
19 %and = and i64 %a, 65534
20 ret i64 %and
28 %and = and i64 %b, 65535
29 ret i64 %and
37 %and = and i64 %a, 65536
38 ret i64 %and
46 %and = and i64 %a, 4294967294
47 ret i64 %and
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Drisbg-04.ll12 %and = and i32 %shr, 1
13 ret i32 %and
16 ; ...and again with i64.
22 %and = and i64 %shr, 1
23 ret i64 %and
32 %and = and i32 %shr, 12
33 ret i32 %and
36 ; ...and again with i64.
42 %and = and i64 %shr, 12
43 ret i64 %and
[all …]
Dand-02.ll10 %and = and i32 %a, 1
11 ret i32 %and
19 %and = and i32 %b, 1
20 ret i32 %and
28 %and = and i32 %b, 4
29 ret i32 %and
37 %and = and i32 %a, 5
38 ret i32 %and
46 %and = and i32 %b, 5
47 ret i32 %and
[all …]
Drisbg-01.ll12 %and = and i32 %shr, 1
13 ret i32 %and
16 ; ...and again with i64.
22 %and = and i64 %shr, 1
23 ret i64 %and
32 %and = and i32 %shr, 12
33 ret i32 %and
36 ; ...and again with i64.
42 %and = and i64 %shr, 12
43 ret i64 %and
[all …]
Dand-04.ll10 %and = and i64 %a, 1
11 ret i64 %and
19 %and = and i64 %a, 65534
20 ret i64 %and
28 %and = and i64 %b, 65535
29 ret i64 %and
37 %and = and i64 %a, 65536
38 ret i64 %and
46 %and = and i64 %a, 4294967294
47 ret i64 %and
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstSimplify/
Dand-icmps-same-ops.ll14 %and = and i1 %cmp1, %cmp2
15 ret i1 %and
24 %and = and i1 %cmp1, %cmp2
25 ret i1 %and
35 %and = and i1 %cmp1, %cmp2
36 ret i1 %and
45 %and = and i1 %cmp1, %cmp2
46 ret i1 %and
56 %and = and i1 %cmp1, %cmp2
57 ret i1 %and
[all …]
/external/scapy/scapy/contrib/
Dgtp_v2.uts10 gtp.dport == 2123 and gtp.gtp_type == 1
14 gtp.dport == 2123 and gtp.seq == 12345 and gtp.gtp_type == 1 and gtp.T == 0
20 gtp.dport == 2123 and gtp.teid == 2807 and gtp.seq == 12345
45 ie.ietype == 1 and ie.IMSI == b'2080112345670000'
56 ie.ietype == 2 and ie.Cause == 16 and ie.PCE == 1 and ie.BCE == 0 and ie.CS == 0
61 ie.ietype == 2 and ie.Cause == 16 and ie.PCE == 0 and ie.BCE == 1 and ie.CS == 0
66 ie.ietype == 2 and ie.Cause == 16 and ie.PCE == 0 and ie.BCE == 0 and ie.CS == 1
72 ie.ietype == 3 and ie.restart_counter == 13
77 ie.ietype == 3 and ie.restart_counter == 17
87 ie.ietype == 71 and ie.APN == b'aaaaaaaaaaaaaaaaaaaaaaaaa'
[all …]
Dgtp.uts21 gtp.dport == 2123 and gtp.teid == 2807 and len(gtp.IE_list) == 5
44 ie.ietype == 1 and ie.CauseValue == 128
48 ie.ietype == 1 and ie.CauseValue == 194
54 ie.ietype == 2 and ie.imsi == b'2080112345670000'
58 ie.ietype == 2 and ie.imsi == b'208103397660354'
64 ie.ietype == 3 and ie.MCC == b'234' and ie.MNC == b'02' and ie.LAC == 1234 and ie.RAC == 123
68 ie.ietype == 3 and ie.MCC == b'234' and ie.MNC == b'02' and ie.LAC == 1234 and ie.RAC == 123
74 ie.ietype == 14 and ie.restart_counter == 14
78 ie.ietype == 14 and ie.restart_counter == 14
84 ie.ietype == 15 and ie.SelectionMode == 252
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dmasked-merge-add.ll21 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]]
23 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[NEG]], [[Y:%.*]]
27 %and = and i32 %x, %m
29 %and1 = and i32 %neg, %y
30 %ret = add i32 %and, %and1
36 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], [[M:%.*]]
38 ; CHECK-NEXT: [[AND1:%.*]] = and <2 x i32> [[NEG]], [[Y:%.*]]
42 %and = and <2 x i32> %x, %m
44 %and1 = and <2 x i32> %neg, %y
45 %ret = add <2 x i32> %and, %and1
[all …]
Dmasked-merge-xor.ll21 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]]
23 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[NEG]], [[Y:%.*]]
27 %and = and i32 %x, %m
29 %and1 = and i32 %neg, %y
30 %ret = xor i32 %and, %and1
36 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], [[M:%.*]]
38 ; CHECK-NEXT: [[AND1:%.*]] = and <2 x i32> [[NEG]], [[Y:%.*]]
42 %and = and <2 x i32> %x, %m
44 %and1 = and <2 x i32> %neg, %y
45 %ret = xor <2 x i32> %and, %and1
[all …]
Dmasked-merge-or.ll21 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[M:%.*]]
23 ; CHECK-NEXT: [[AND1:%.*]] = and i32 [[NEG]], [[Y:%.*]]
27 %and = and i32 %x, %m
29 %and1 = and i32 %neg, %y
30 %ret = or i32 %and, %and1
36 ; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[X:%.*]], [[M:%.*]]
38 ; CHECK-NEXT: [[AND1:%.*]] = and <2 x i32> [[NEG]], [[Y:%.*]]
42 %and = and <2 x i32> %x, %m
44 %and1 = and <2 x i32> %neg, %y
45 %ret = or <2 x i32> %and, %and1
[all …]
/external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/
Dbit-checks.ll8 %and = and i32 %argc, 1 ; <i32> [#uses=1]
9 %tobool = icmp ne i32 %and, 0 ; <i1> [#uses=1]
10 %and2 = and i32 %argc, 2 ; <i32> [#uses=1]
12 %or.cond = and i1 %tobool, %tobool3 ; <i1> [#uses=1]
19 %and = and i32 %argc, 1 ; <i32> [#uses=1]
20 %tobool = icmp eq i32 %and, 0 ; <i1> [#uses=1]
21 %and2 = and i32 %argc, 2 ; <i32> [#uses=1]
35 %and = and i32 %argc, 7 ; <i32> [#uses=1]
36 %tobool = icmp eq i32 %and, 0 ; <i1> [#uses=1]
37 %and2 = and i32 %argc, 48 ; <i32> [#uses=1]
[all …]
/external/llvm/test/Transforms/InstCombine/
Dbit-checks.ll8 %and = and i32 %argc, 1 ; <i32> [#uses=1]
9 %tobool = icmp ne i32 %and, 0 ; <i1> [#uses=1]
10 %and2 = and i32 %argc, 2 ; <i32> [#uses=1]
12 %or.cond = and i1 %tobool, %tobool3 ; <i1> [#uses=1]
19 %and = and i32 %argc, 1 ; <i32> [#uses=1]
20 %tobool = icmp eq i32 %and, 0 ; <i1> [#uses=1]
21 %and2 = and i32 %argc, 2 ; <i32> [#uses=1]
35 %and = and i32 %argc, 7 ; <i32> [#uses=1]
36 %tobool = icmp eq i32 %and, 0 ; <i1> [#uses=1]
37 %and2 = and i32 %argc, 48 ; <i32> [#uses=1]
[all …]

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