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Searched refs:and3 (Results 1 – 25 of 52) sorted by relevance

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/external/llvm/test/CodeGen/X86/
Drotate4.ll14 %and3 = and i32 %0, 31
15 %shr = lshr i32 %a, %and3
28 %and3 = and i32 %0, 31
29 %shr = shl i32 %a, %and3
42 %and3 = and i64 %0, 63
43 %shr = lshr i64 %a, %and3
56 %and3 = and i64 %0, 63
57 %shr = shl i64 %a, %and3
75 %and3 = and i32 %0, 31
76 %shr = lshr i32 %a, %and3
[all …]
DtargetLoweringGeneric.ll18 %and3 = and i32 %i32In1, 1362779777
21 %xor3 = xor i32 %and3, %and2
/external/llvm/test/CodeGen/PowerPC/
Dppc-crbits-onoff.ll10 %and3 = and i1 %tobool, %lnot
11 %and = zext i1 %and3 to i32
27 %and3 = and i1 %tobool, %lnot
28 %and = zext i1 %and3 to i32
Dbperm.ll163 %and3 = and i64 %1, 405323966463344640
164 %or4 = or i64 %and, %and3
184 %and3 = and i64 %1, 2473599172608
185 %or4 = or i64 %and, %and3
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dppc-crbits-onoff.ll11 %and3 = and i1 %tobool, %lnot
12 %and = zext i1 %and3 to i32
34 %and3 = and i1 %tobool, %lnot
35 %and = zext i1 %and3 to i32
Dpr33093.ll48 %and3 = and i32 %shr2, 858993459
51 %or6 = or i32 %and3, %shl5
134 %and3 = and i64 %shr2, 3689348814741910323
137 %or6 = or i64 %and3, %shl5
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Drotate4.ll25 %and3 = and i32 %t0, 31
26 %shr = lshr i32 %a, %and3
48 %and3 = and i32 %t0, 31
49 %shr = shl i32 %a, %and3
108 %and3 = and i64 %t0, 63
109 %shr = lshr i64 %a, %and3
168 %and3 = and i64 %t0, 63
169 %shr = shl i64 %a, %and3
193 %and3 = and i32 %t0, 31
194 %shr = lshr i32 %a, %and3
[all …]
DtargetLoweringGeneric.ll18 %and3 = and i32 %i32In1, 1362779777
21 %xor3 = xor i32 %and3, %and2
Dpr34137.ll33 %and3 = and i32 %conv, %and
34 store i32 %and3, i32* %a, align 4
/external/swiftshader/third_party/LLVM/test/CodeGen/SystemZ/
D2009-06-02-And32Imm.ll10 %and3 = and i32 %conv, -4096 ; <i32> [#uses=1]
12 %conv5 = or i32 %and6, %and3 ; <i32> [#uses=1]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/
Dtwoaddr-sink.ll11 %and3 = and i32 %res1, 127
13 %res2 = call i32 asm "stepb $1, $2, $3", "=r,h,h,0"(i32 %res1, i32 %and3, i32 %and4)
/external/llvm/test/CodeGen/Mips/
Dmips16fpe.ll268 %and3 = and i1 %cmp, %cmp1
269 %and = zext i1 %and3 to i32
283 %and3 = and i1 %cmp, %cmp1
284 %and = zext i1 %and3 to i32
330 %and3 = and i1 %cmp, %cmp1
331 %and = zext i1 %and3 to i32
345 %and3 = and i1 %cmp, %cmp1
346 %and = zext i1 %and3 to i32
Dmips64extins.ll36 %and3 = and i64 %i, -261889
37 %or = or i64 %and3, %and
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dmips16fpe.ll268 %and3 = and i1 %cmp, %cmp1
269 %and = zext i1 %and3 to i32
283 %and3 = and i1 %cmp, %cmp1
284 %and = zext i1 %and3 to i32
330 %and3 = and i1 %cmp, %cmp1
331 %and = zext i1 %and3 to i32
345 %and3 = and i1 %cmp, %cmp1
346 %and = zext i1 %and3 to i32
Dmips64extins.ll36 %and3 = and i64 %i, -261889
37 %or = or i64 %and3, %and
/external/llvm/test/CodeGen/Hexagon/
Dmemops.ll52 %and3 = and i8 %0, %x
53 store i8 %and3, i8* %p, align 1
132 %and3 = and i8 %0, %x
133 store i8 %and3, i8* %add.ptr, align 1
214 %and3 = and i8 %0, %x
215 store i8 %and3, i8* %add.ptr, align 1
291 %and3 = and i8 %0, %x
292 store i8 %and3, i8* %p, align 1
371 %and3 = and i8 %0, %x
372 store i8 %and3, i8* %add.ptr, align 1
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dmemops.ll57 %and3 = and i8 %0, %x
58 store i8 %and3, i8* %p, align 1
144 %and3 = and i8 %0, %x
145 store i8 %and3, i8* %add.ptr, align 1
233 %and3 = and i8 %0, %x
234 store i8 %and3, i8* %add.ptr, align 1
317 %and3 = and i8 %0, %x
318 store i8 %and3, i8* %p, align 1
404 %and3 = and i8 %0, %x
405 store i8 %and3, i8* %add.ptr, align 1
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb2/
Dbfi.ll59 %and3 = or i32 %b.masked, %and
60 ret i32 %and3
/external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/
Dbfi.ll59 %and3 = or i32 %b.masked, %and
60 ret i32 %and3
/external/llvm/test/CodeGen/Thumb2/
Dbfi.ll59 %and3 = or i32 %b.masked, %and
60 ret i32 %and3
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Doptimize-imm.ll28 ; CHECK-LABEL: and3:
31 define i32 @and3(i32 %a) {
/external/llvm/test/Transforms/LoopVectorize/
Dcalloc.ll30 %and3 = xor i64 %neg, 4
31 %sh_prom = trunc i64 %and3 to i32
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopVectorize/
Dcalloc.ll29 %and3 = xor i64 %neg, 4
30 %sh_prom = trunc i64 %and3 to i32
/external/llvm/test/Transforms/ConstantHoisting/ARM/
Dconst-addr-no-neg-offset.ll24 %and3 = and i32 %4, -8323073
25 store volatile i32 %and3, i32* inttoptr (i32 1073876996 to i32*), align 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/ConstantHoisting/ARM/
Dconst-addr-no-neg-offset.ll24 %and3 = and i32 %4, -8323073
25 store volatile i32 %and3, i32* inttoptr (i32 1073876996 to i32*), align 4

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