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Searched refs:andc (Results 1 – 25 of 47) sorted by relevance

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/external/u-boot/arch/powerpc/cpu/mpc86xx/
Dcache.S76 andc r3,r3,r5
103 andc r3,r3,r5 /* align r3 down to cache line */
177 andc r3, r3, r5
196 andc r3, r3, r5
213 andc r3, r3, r5
229 andc r3, r3, r5
256 andc r3, r3, r5
259 andc r3, r3, r5 /* no enable, no invalidate */
Dstart.S479 andc r3, r3, r0
493 andc r23,r23,r22
517 andc r28,r28,r4
710 andc r3,r3,r0
857 andc r7,r7,r8
955 andc r0,r0,r3
967 andc r0,r0,r3
Drelease.S102 andc r3, r3, r5
121 andc r3, r3, r5
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dandc.ll7 ; CHECK-NEXT: andc 3, 4, 3
20 ; CHECK-NEXT: andc 3, 4, 3
34 ; CHECK-NEXT: andc 3, 4, 3
Dvariable_elem_vec_extracts.ll16 ; CHECK-DAG: andc [[MASKREG:[0-9]+]], [[TRUNCREG]], 5
34 ; CHECK-BE-DAG: andc [[ANDCREG:[0-9]+]], [[IMMREG]], 5
50 ; CHECK-DAG: andc [[MASKREG:[0-9]+]], [[TRUNCREG]], 5
96 ; CHECK: andc [[MASKREG:[0-9]+]], [[TRUNCREG]], 5
Datomic-minmax.ll249 ; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
276 ; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
301 ; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
326 ; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
352 ; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
378 ; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
402 ; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
426 ; CHECK: andc [[NOLDV:[0-9]+]], [[OLDV]], [[M]]
Dp8-scalar_vector_conversions.ll542 ; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM7]]
548 ; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM8]]
570 ; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM7]]
576 ; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM8]]
822 ; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM3]]
828 ; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM4]]
852 ; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM3]]
858 ; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM4]]
DPR35812-neg-cmpxchg.ll55 ; CHECK-P7: andc 9, 9, 5
Deqv-andc-orc-nor.ll4 ; RUN: grep andc | count 3
/external/u-boot/arch/powerpc/lib/
Dppccache.S69 andc r3,r3,r5
93 andc r3,r3,r5
/external/llvm/test/CodeGen/PowerPC/
Dvariable_elem_vec_extracts.ll16 ; CHECK-DAG: andc [[MASKREG:[0-9]+]], [[TRUNCREG]], 5
34 ; CHECK-BE-DAG: andc [[ANDCREG:[0-9]+]], [[IMMREG]], 5
50 ; CHECK-DAG: andc [[MASKREG:[0-9]+]], [[TRUNCREG]], 5
96 ; CHECK: andc [[MASKREG:[0-9]+]], [[TRUNCREG]], 5
Dandc.ll3 ; TODO: These could use 'andc'.
Dp8-scalar_vector_conversions.ll686 ; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM7]]
692 ; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM8]]
720 ; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM7]]
726 ; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM8]]
1038 ; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM3]]
1044 ; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM4]]
1074 ; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM3]]
1080 ; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM4]]
Deqv-andc-orc-nor.ll4 ; RUN: grep andc | count 3
/external/swiftshader/third_party/LLVM/test/CodeGen/CellSPU/
Dintrinsics_logical.ll3 ; RUN: grep andc %t1.s | count 5
8 declare <4 x i32> @llvm.spu.si.andc(<4 x i32>, <4 x i32>)
34 call <4 x i32> @llvm.spu.si.andc(<4 x i32> %A, <4 x i32> %B)
/external/u-boot/arch/powerpc/cpu/mpc83xx/
Dstart.S113 andc r3, r3, r0
430 andc r23,r23,r22
453 andc r28,r28,r4
741 andc r3, r3, r4
754 andc r3, r3, r4
770 andc r3, r3, r5
782 andc r3, r3, r5
903 andc r3,r3,r0
1053 andc r3, r3, r7 /* (if it was on) */
1104 andc r3, r3, r5 /* no invalidate, unlock */
/external/capstone/suite/MC/PowerPC/
Dppc64-encoding.s.cs147 0x7c,0x62,0x20,0x78 = andc 2, 3, 4
148 0x7c,0x62,0x20,0x79 = andc. 2, 3, 4
/external/u-boot/arch/powerpc/cpu/mpc8xx/
Dstart.S270 andc r23,r23,r22
294 andc r28,r28,r4
395 andc r3,r3,r0
/external/u-boot/arch/powerpc/cpu/mpc85xx/
Dstart.S157 andc r4, r3, r2
404 andc r3, r3, r2 /* Clear the TSIZE bits */
419 andc r2, r2, r3
432 andc r2, r2, r3
1318 andc r28,r28,r4
1386 andc r0,r0,r3
1417 andc r3,r3,r4
1622 andc r3,r3,r0
/external/llvm/test/MC/PowerPC/
Dppc64-encoding.s632 # CHECK-BE: andc 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x78]
633 # CHECK-LE: andc 2, 3, 4 # encoding: [0x78,0x20,0x62,0x7c]
634 andc 2, 3, 4
635 # CHECK-BE: andc. 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x79]
636 # CHECK-LE: andc. 2, 3, 4 # encoding: [0x79,0x20,0x62,0x7c]
637 andc. 2, 3, 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/
Dppc64-encoding.s718 # CHECK-BE: andc 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x78]
719 # CHECK-LE: andc 2, 3, 4 # encoding: [0x78,0x20,0x62,0x7c]
720 andc 2, 3, 4
721 # CHECK-BE: andc. 2, 3, 4 # encoding: [0x7c,0x62,0x20,0x79]
722 # CHECK-LE: andc. 2, 3, 4 # encoding: [0x79,0x20,0x62,0x7c]
723 andc. 2, 3, 4
/external/swiftshader/third_party/LLVM/test/CodeGen/PowerPC/
Deqv-andc-orc-nor.ll4 ; RUN: grep andc | count 3
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/
Dppc64le-encoding.txt499 # CHECK: andc 2, 3, 4
502 # CHECK: andc. 2, 3, 4
/external/llvm/test/MC/Disassembler/PowerPC/
Dppc64-encoding.txt508 # CHECK: andc 2, 3, 4
511 # CHECK: andc. 2, 3, 4
Dppc64le-encoding.txt487 # CHECK: andc 2, 3, 4
490 # CHECK: andc. 2, 3, 4

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