| /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
| D | vector-select.ll | 51 ; MIPS32: andi [[T3]],[[T3]],0xff
52 ; MIPS32: andi [[T3]],[[T3]],0x1
54 ; MIPS32: andi [[T2]],[[T2]],0xff
56 ; MIPS32: andi [[T1]],[[T1]],0xff
58 ; MIPS32: andi [[T1]],[[T1]],0xff
64 ; MIPS32: andi [[T14]],[[T14]],0xff
65 ; MIPS32: andi [[T14]],[[T14]],0x1
68 ; MIPS32: andi [[T3]],[[T3]],0xff
71 ; MIPS32: andi [[T2]],[[T2]],0xff
73 ; MIPS32: andi [[T2]],[[T2]],0xff
[all …]
|
| D | vector-cast.ll | 37 ; MIPS32: andi t2,t2,0xff
38 ; MIPS32: andi t2,t2,0x1
41 ; MIPS32: andi t2,t2,0xff
47 ; MIPS32: andi v0,v0,0xff
48 ; MIPS32: andi v0,v0,0x1
51 ; MIPS32: andi v0,v0,0xff
59 ; MIPS32: andi t2,t2,0xff
60 ; MIPS32: andi t2,t2,0x1
63 ; MIPS32: andi t2,t2,0xff
70 ; MIPS32: andi a0,a0,0x1
[all …]
|
| D | vector-icmp.ll | 38 ; MIPS32: andi [[T4]],[[T4]],0x1
41 ; MIPS32: andi [[T5]],[[T5]],0x1
44 ; MIPS32: andi [[T6]],[[T6]],0x1
47 ; MIPS32: andi [[T7]],[[T7]],0x1
285 ; MIPS32: andi [[T4:.*]],a0,0x1
286 ; MIPS32: andi [[T0]],[[T0]],0x1
291 ; MIPS32: andi [[T5:.*]],a1,0x1
292 ; MIPS32: andi [[T1]],[[T1]],0x1
297 ; MIPS32: andi [[T6:.*]],a2,0x1
298 ; MIPS32: andi [[T2]],[[T2]],0x1
[all …]
|
| D | 8bit.pnacl.ll | 37 ; MIPS32: andi {{.*}},0xff
53 ; MIPS32: andi {{.*}},0xff
70 ; MIPS32: andi {{.*}},0xff
86 ; MIPS32: andi {{.*}},0xff
103 ; MIPS32: andi {{.*}},0xff
122 ; MIPS32: andi {{.*}},0xff
141 ; MIPS32: andi {{.*}},0xff
159 ; MIPS32: andi {{.*}},0xff
180 ; MIPS32: andi {{.*}},0xff
199 ; MIPS32: andi {{.*}},0xff
[all …]
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | and.ll | 168 ; GP32: andi $2, $4, 4
170 ; GP64: andi $2, $4, 4
182 ; GP32: andi $2, $4, 4
184 ; GP64: andi $2, $4, 4
196 ; GP32: andi $2, $4, 4
198 ; GP64: andi $2, $4, 4
210 ; GP32: andi $3, $5, 4
213 ; GP64: andi $2, $4, 4
218 ; MM64: andi $2, $4, 4
228 ; GP32: andi $5, $7, 4
[all …]
|
| D | urem.ll | 40 ; NOT-R6: andi $[[T0:[0-9]+]], $5, 1
41 ; NOT-R6: andi $[[T1:[0-9]+]], $4, 1
48 ; R6: andi $[[T0:[0-9]+]], $5, 1
49 ; R6: andi $[[T1:[0-9]+]], $4, 1
78 ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 255
79 ; NOT-R2-R6: andi $[[T1:[0-9]+]], $4, 255
86 ; R2-R5: andi $[[T0:[0-9]+]], $5, 255
87 ; R2-R5: andi $[[T1:[0-9]+]], $4, 255
93 ; R6: andi $[[T0:[0-9]+]], $5, 255
94 ; R6: andi $[[T1:[0-9]+]], $4, 255
[all …]
|
| D | select-int.ll | 37 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
45 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
49 ; SEL: andi $[[T0:[0-9]+]], $4, 1
72 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
80 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
84 ; SEL: andi $[[T0:[0-9]+]], $4, 1
107 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
115 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
119 ; SEL: andi $[[T0:[0-9]+]], $4, 1
142 ; M2: andi $[[T0:[0-9]+]], $4, 1
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AVR/ |
| D | inst-andi.s | 6 andi r16, 255
7 andi r29, 190
8 andi r22, 172
9 andi r27, 92
11 andi r20, BAR
13 ; CHECK: andi r16, 255 ; encoding: [0x0f,0x7f]
14 ; CHECK: andi r29, 190 ; encoding: [0xde,0x7b]
15 ; CHECK: andi r22, 172 ; encoding: [0x6c,0x7a]
16 ; CHECK: andi r27, 92 ; encoding: [0xbc,0x75]
18 ; CHECK: andi r20, BAR ; encoding: [0x40'A',0x70]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | and.ll | 409 ; MIPS-NEXT: andi $2, $4, 4
414 ; MIPS32R2-NEXT: andi $2, $4, 4
419 ; MIPS32R6-NEXT: andi $2, $4, 4
424 ; MIPS64-NEXT: andi $2, $4, 4
429 ; MIPS64R2-NEXT: andi $2, $4, 4
434 ; MIPS64R6-NEXT: andi $2, $4, 4
454 ; MIPS-NEXT: andi $2, $4, 4
459 ; MIPS32R2-NEXT: andi $2, $4, 4
464 ; MIPS32R6-NEXT: andi $2, $4, 4
469 ; MIPS64-NEXT: andi $2, $4, 4
[all …]
|
| D | urem.ll | 38 ; NOT-R6: andi $[[T0:[0-9]+]], $5, 1
39 ; NOT-R6: andi $[[T1:[0-9]+]], $4, 1
43 ; NOT-R6: andi $[[T0]], $[[T0]], 1
46 ; R6: andi $[[T0:[0-9]+]], $5, 1
47 ; R6: andi $[[T1:[0-9]+]], $4, 1
76 ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 255
77 ; NOT-R2-R6: andi $[[T1:[0-9]+]], $4, 255
84 ; R2-R5: andi $[[T0:[0-9]+]], $5, 255
85 ; R2-R5: andi $[[T1:[0-9]+]], $4, 255
91 ; R6: andi $[[T0:[0-9]+]], $5, 255
[all …]
|
| D | select-int.ll | 37 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
46 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
50 ; SEL: andi $[[T0:[0-9]+]], $4, 1
73 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
82 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
86 ; SEL: andi $[[T0:[0-9]+]], $4, 1
109 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
118 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
122 ; SEL: andi $[[T0:[0-9]+]], $4, 1
146 ; M2: andi $[[T0:[0-9]+]], $4, 1
[all …]
|
| D | ashr.ll | 91 ; MIPS-NEXT: andi $1, $5, 255
97 ; MIPS32-NEXT: andi $1, $5, 255
103 ; 32R2-NEXT: andi $1, $5, 255
109 ; 32R6-NEXT: andi $1, $5, 255
115 ; MIPS3-NEXT: andi $1, $5, 255
121 ; MIPS64-NEXT: andi $1, $5, 255
127 ; MIPS64R2-NEXT: andi $1, $5, 255
133 ; MIPS64R6-NEXT: andi $1, $5, 255
149 ; FIXME: The andi instruction is redundant.
157 ; MIPS-NEXT: andi $1, $5, 65535
[all …]
|
| D | lshr.ll | 99 ; MIPS2-NEXT: andi $2, $1, 255
105 ; MIPS32-NEXT: andi $2, $1, 255
111 ; MIPS32R2-NEXT: andi $2, $1, 255
117 ; MIPS32R6-NEXT: andi $2, $1, 255
123 ; MIPS3-NEXT: andi $2, $1, 255
129 ; MIPS4-NEXT: andi $2, $1, 255
135 ; MIPS64-NEXT: andi $2, $1, 255
141 ; MIPS64R2-NEXT: andi $2, $1, 255
147 ; MIPS64R6-NEXT: andi $2, $1, 255
171 ; MIPS2-NEXT: andi $2, $1, 65535
[all …]
|
| D | shl.ll | 97 ; MIPS2-NEXT: andi $1, $5, 255
105 ; MIPS32-NEXT: andi $1, $5, 255
113 ; MIPS32R2-NEXT: andi $1, $5, 255
120 ; MIPS32R6-NEXT: andi $1, $5, 255
127 ; MIPS3-NEXT: andi $1, $5, 255
135 ; MIPS4-NEXT: andi $1, $5, 255
143 ; MIPS64-NEXT: andi $1, $5, 255
151 ; MIPS64R2-NEXT: andi $1, $5, 255
158 ; MIPS64R6-NEXT: andi $1, $5, 255
185 ; MIPS2-NEXT: andi $1, $5, 65535
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AVR/ |
| D | PR31345.ll | 7 ; CHECK: andi {{r[0-9]+}}, 0
8 ; CHECK-NOT: andi {{r[0-9]+}}, 255
15 ; CHECK: andi {{r[0-9]+}}, 179
16 ; CHECK-NOT: andi {{r[0-9]+}}, 255
23 ; CHECK-NOT: andi {{r[0-9]+}}, 255
24 ; CHECK: andi {{r[0-9]+}}, 0
31 ; CHECK-NOT: andi {{r[0-9]+}}, 255
32 ; CHECK: andi {{r[0-9]+}}, 179
39 ; CHECK-NOT: andi {{r[0-9]+}}, 255
40 ; CHECK-NOT: andi {{r[0-9]+}}, 255
[all …]
|
| D | and.ll | 12 ; CHECK: andi r24, 5
27 ; CHECK: andi r24, 210
28 ; CHECK: andi r25, 4
45 ; CHECK: andi r22, 21
46 ; CHECK: andi r23, 205
47 ; CHECK: andi r24, 91
48 ; CHECK: andi r25, 7
69 ; CHECK: andi r18, 253
71 ; CHECK-NOT: andi r19, 255
72 ; CHECK: andi r20, 155
[all …]
|
| D | ctpop.ll | 14 ; CHECK: andi {{.*}}[[SCRATCH]], 85
17 ; CHECK: andi {{.*}}[[SCRATCH]], 51
20 ; CHECK: andi {{.*}}[[RESULT]], 51
28 ; CHECK: andi {{.*}}[[SCRATCH]], 15
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/Fast-ISel/ |
| D | bricmpi1.ll | 6 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
7 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
23 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
24 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
40 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
41 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
58 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
59 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
76 ; CHECK: andi $[[REG0:[0-9]+]], $4, 1
77 ; CHECK: andi $[[REG1:[0-9]+]], $5, 1
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | select_const.ll | 73 ; ISEL-NEXT: andi. 3, 3, 1
82 ; NO_ISEL-NEXT: andi. 3, 3, 1
98 ; ISEL-NEXT: andi. 3, 3, 1
107 ; NO_ISEL-NEXT: andi. 3, 3, 1
123 ; ISEL-NEXT: andi. 3, 3, 1
132 ; NO_ISEL-NEXT: andi. 3, 3, 1
150 ; ISEL-NEXT: andi. 3, 3, 1
159 ; NO_ISEL-NEXT: andi. 3, 3, 1
174 ; ISEL-NEXT: andi. 3, 3, 1
183 ; NO_ISEL-NEXT: andi. 3, 3, 1
[all …]
|
| D | crbit-asm.ll | 17 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
20 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
40 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
43 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
56 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
59 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/MBlaze/ |
| D | shift.ll | 13 ; FUN: andi
30 ; FUN: andi
33 ; SHT-NOT: andi
49 ; FUN: andi
66 ; FUN: andi
69 ; SHT-NOT: andi
85 ; FUN: andi
88 ; SHT-NOT: andi
103 ; FUN: andi
106 ; SHT-NOT: andi
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
| D | fcmp.ll | 50 ; 32-CMP-DAG: andi $2, $[[T1]], 1
54 ; 64-CMP-DAG: andi $2, $[[T1]], 1
83 ; 32-CMP-DAG: andi $2, $[[T1]], 1
87 ; 64-CMP-DAG: andi $2, $[[T1]], 1
116 ; 32-CMP-DAG: andi $2, $[[T1]], 1
120 ; 64-CMP-DAG: andi $2, $[[T1]], 1
149 ; 32-CMP-DAG: andi $2, $[[T1]], 1
153 ; 64-CMP-DAG: andi $2, $[[T1]], 1
182 ; 32-CMP-DAG: andi $2, $[[T1]], 1
186 ; 64-CMP-DAG: andi $2, $[[T1]], 1
[all …]
|
| /external/llvm/test/CodeGen/Mips/ |
| D | fcmp.ll | 52 ; 32-CMP-DAG: andi $2, $[[T1]], 1
56 ; 64-CMP-DAG: andi $2, $[[T1]], 1
86 ; 32-CMP-DAG: andi $2, $[[T1]], 1
90 ; 64-CMP-DAG: andi $2, $[[T1]], 1
120 ; 32-CMP-DAG: andi $2, $[[T1]], 1
124 ; 64-CMP-DAG: andi $2, $[[T1]], 1
154 ; 32-CMP-DAG: andi $2, $[[T1]], 1
158 ; 64-CMP-DAG: andi $2, $[[T1]], 1
188 ; 32-CMP-DAG: andi $2, $[[T1]], 1
192 ; 64-CMP-DAG: andi $2, $[[T1]], 1
[all …]
|
| /external/swiftshader/third_party/subzero/tests_lit/assembler/mips32/ |
| D | encoding_test_fcmp.ll | 35 ; ASM-NEXT: andi $v0, $v0, 1
40 ; DIS-NEXT: 4: 30420001 andi v0,v0,0x1
68 ; ASM-NEXT: andi $v0, $v0, 1
73 ; DIS-NEXT: 14: 30420001 andi v0,v0,0x1
103 ; ASM-NEXT: andi $v0, $v0, 1
110 ; DIS-NEXT: 2c: 30420001 andi v0,v0,0x1
148 ; ASM-NEXT: andi $v0, $v0, 1
155 ; DIS-NEXT: 4c: 30420001 andi v0,v0,0x1
193 ; ASM-NEXT: andi $v0, $v0, 1
200 ; DIS-NEXT: 6c: 30420001 andi v0,v0,0x1
[all …]
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | crbit-asm.ll | 14 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
17 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
33 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
36 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
49 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
52 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
|