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Searched refs:anv_batch_emit (Results 1 – 10 of 10) sorted by relevance

/external/mesa3d/src/intel/vulkan/
DgenX_gpu_memcpy.c71 anv_batch_emit(&cmd_buffer->batch, GENX(MI_COPY_MEM_MEM), cp) { in genX()
80 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_MEM), load) { in genX()
84 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), store) { in genX()
162 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF_SGVS), sgvs); in genX()
166 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VS), vs); in genX()
167 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_HS), hs); in genX()
168 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_TE), te); in genX()
169 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_DS), DS); in genX()
170 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_GS), gs); in genX()
171 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_PS), gs); in genX()
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DgenX_state.c49 anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) { in gen10_emit_wa_cs_stall_flush()
69 anv_batch_emit(batch, GENX(PIPE_CONTROL), pc) { in gen10_emit_wa_lri_to_cache_mode_zero()
84 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in gen10_emit_wa_lri_to_cache_mode_zero()
103 anv_batch_emit(&batch, GENX(PIPELINE_SELECT), ps) { in genX()
118 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in genX()
130 anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in genX()
136 anv_batch_emit(&batch, GENX(3DSTATE_AA_LINE_PARAMETERS), aa); in genX()
138 anv_batch_emit(&batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) { in genX()
148 anv_batch_emit(&batch, GENX(3DSTATE_WM_CHROMAKEY), ck); in genX()
157 anv_batch_emit(&batch, GENX(3DSTATE_SAMPLE_PATTERN), sp) { in genX()
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DgenX_query.c302 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in emit_ps_depth_count()
317 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in emit_query_availability()
339 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) { in emit_zero_queries()
359 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdm) { in genX()
393 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), lrm) { in emit_pipeline_stat()
397 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), lrm) { in emit_pipeline_stat()
419 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
455 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
508 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), srm) { in genX()
512 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_REGISTER_MEM), srm) { in genX()
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Dgen8_cmd_buffer.c73 anv_batch_emit(&cmd_buffer->batch, in gen8_cmd_buffer_emit_viewport()
102 anv_batch_emit(&cmd_buffer->batch, in gen8_cmd_buffer_emit_depth_viewport()
126 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
138 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in genX()
151 anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in genX()
165 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
446 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) { in genX()
496 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) { in genX()
536 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_VF), vf) { in genX()
566 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) { in genX()
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DgenX_pipeline.c156 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_INSTANCING), vfi) { in emit_vertex_input()
202 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_SGVS), sgvs) { in emit_vertex_input()
228 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VF_INSTANCING), vfi) { in emit_vertex_input()
268 anv_batch_emit(batch, GEN7_PIPE_CONTROL, pc) { in genX()
276 anv_batch_emit(batch, GENX(3DSTATE_URB_VS), urb) { in genX()
308 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE), sbe); in emit_3dstate_sbe()
310 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SBE_SWIZ), sbe); in emit_3dstate_sbe()
553 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_MULTISAMPLE), ms) { in emit_ms_state()
585 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_SAMPLE_MASK), sm) { in emit_ms_state()
982 anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS_BLEND), blend) {
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DgenX_cmd_buffer.c39 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) { in emit_lrm()
48 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), lri) { in emit_lri()
58 anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_REG), lrr) { in emit_lrr()
77 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
83 anv_batch_emit(&cmd_buffer->batch, GENX(STATE_BASE_ADDRESS), sba) { in genX()
160 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in genX()
426 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) { in genX()
455 anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) { in genX()
499 anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) { in init_fast_clear_state_entry()
1055 anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) { in emit_isp_disable()
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Dgen7_cmd_buffer.c88 anv_batch_emit(&cmd_buffer->batch, in gen7_cmd_buffer_emit_scissor()
195 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CC_STATE_POINTERS), ccp) { in genX()
224 anv_batch_emit(&cmd_buffer->batch, in genX()
237 anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF, vf) { in genX()
243 anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_INDEX_BUFFER), ib) { in genX()
Danv_batch_chain.c480 anv_batch_emit(&cmd_buffer->batch, GEN8_MI_BATCH_BUFFER_START, bbs) { in emit_batch_buffer_start()
806 anv_batch_emit(&cmd_buffer->batch, GEN8_MI_BATCH_BUFFER_END, bbe); in anv_cmd_buffer_end_batch_buffer()
810 anv_batch_emit(&cmd_buffer->batch, GEN8_MI_NOOP, noop); in anv_cmd_buffer_end_batch_buffer()
Danv_device.c1249 anv_batch_emit(&batch, GEN7_MI_BATCH_BUFFER_END, bbe); in anv_device_init_trivial_batch()
1250 anv_batch_emit(&batch, GEN7_MI_NOOP, noop); in anv_device_init_trivial_batch()
1707 anv_batch_emit(&batch, GEN7_MI_BATCH_BUFFER_END, bbe); in anv_DeviceWaitIdle()
1708 anv_batch_emit(&batch, GEN7_MI_NOOP, noop); in anv_DeviceWaitIdle()
Danv_private.h1100 #define anv_batch_emit(batch, cmd, name) \ macro