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Searched refs:apll_mdiv (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-exynos/
Dclock_init.h23 unsigned apll_mdiv; member
44 unsigned apll_mdiv; member
Dclock_init_exynos5.c28 .apll_mdiv = 0x96,
45 .apll_mdiv = 0xc8,
60 .apll_mdiv = 0x64,
75 .apll_mdiv = 0x7d,
90 .apll_mdiv = 0x96,
105 .apll_mdiv = 0xaf,
120 .apll_mdiv = 0x1a9,
619 val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv, in exynos5250_system_clock_init()
820 val = set_pll(arm_clk_ratio->apll_mdiv, in exynos5420_system_clock_init()