/external/v8/src/third_party/valgrind/ |
D | valgrind.h | 1017 arg7,arg8,arg9,arg10) \ argument 1032 _argvec[10] = (unsigned long)(arg10); \ 1056 arg6,arg7,arg8,arg9,arg10, \ argument 1072 _argvec[10] = (unsigned long)(arg10); \ 1098 arg6,arg7,arg8,arg9,arg10, \ argument 1114 _argvec[10] = (unsigned long)(arg10); \ 1545 arg7,arg8,arg9,arg10) \ argument 1560 _argvec[10] = (unsigned long)(arg10); \ 1587 arg7,arg8,arg9,arg10,arg11) \ argument 1602 _argvec[10] = (unsigned long)(arg10); \ [all …]
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/external/libchrome/base/third_party/valgrind/ |
D | valgrind.h | 1061 arg7,arg8,arg9,arg10) \ argument 1076 _argvec[10] = (unsigned long)(arg10); \ 1100 arg6,arg7,arg8,arg9,arg10, \ argument 1116 _argvec[10] = (unsigned long)(arg10); \ 1142 arg6,arg7,arg8,arg9,arg10, \ argument 1158 _argvec[10] = (unsigned long)(arg10); \ 1589 arg7,arg8,arg9,arg10) \ argument 1604 _argvec[10] = (unsigned long)(arg10); \ 1631 arg7,arg8,arg9,arg10,arg11) \ argument 1646 _argvec[10] = (unsigned long)(arg10); \ [all …]
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/external/swiftshader/third_party/subzero/crosstest/ |
D | test_calling_conv.cpp | 49 v4f32 arg10 = {22, 23, 24, 25}; in caller_vlvilvfvdviv() local 54 arg6, arg7, arg8, arg9, arg10, in caller_vlvilvfvdviv() 81 v4f32 arg10, int arg11, v4f32 arg12) { in callee_vlvilvfvdviv() argument
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
D | ret.ll | 46 …3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, flo… 71 …3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, flo… 85 …3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, flo… 104 …3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, flo… 133 …3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, flo… 162 …3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, flo…
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D | callee-special-input-vgprs.ll | 243 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, 260 store volatile i32 %arg10, i32 addrspace(1)* undef 342 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, 347 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, 369 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, 386 store volatile i32 %arg10, i32 addrspace(1)* undef 493 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, 514 store volatile i32 %arg10, i32 addrspace(1)* undef 590 i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, 611 store volatile i32 %arg10, i32 addrspace(1)* undef
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D | llvm.AMDGPU.kill.ll | 23 …i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,…
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D | smrd.ll | 109 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo… 123 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo… 140 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo… 155 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo… 170 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo…
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D | ret_jump.ll | 25 …i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,… 76 …i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,…
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D | sgpr-copy.ll | 7 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo… 31 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo… 171 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo… 224 …i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,… 288 …i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,… 324 …i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,…
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D | schedule-kernel-arg-loads.ll | 26 i64 %arg8, i64 %arg9, i64 %arg10, i64 %arg11, i64 %arg12, i64 %arg13, i64 %arg14, i64 %arg15,
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D | si-scheduler.ll | 19 …i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,…
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D | wait.ll | 49 …)* byval %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) #0 {
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D | unigine-liveness-crash.ll | 12 …nreg %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <3 x i32> %arg10, <2 x i32> %arg11,…
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D | vgpr-spill-emergency-stack-slot.ll | 30 …)* byval %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) #0 {
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D | si-sgpr-spill.ll | 27 …i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,… 646 …i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,…
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/external/llvm/test/CodeGen/AMDGPU/ |
D | sgpr-copy.ll | 14 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo… 38 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo… 159 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo… 230 …i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,… 294 …i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,… 324 …i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,…
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D | schedule-kernel-arg-loads.ll | 31 i64 %arg8, i64 %arg9, i64 %arg10, i64 %arg11, i64 %arg12, i64 %arg13, i64 %arg14, i64 %arg15,
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D | si-lod-bias.ll | 9 …i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, flo…
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D | si-scheduler.ll | 19 …i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,…
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D | vgpr-spill-emergency-stack-slot.ll | 29 …)* byval %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) #0 {
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D | si-sgpr-spill.ll | 25 …i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,… 675 …i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11,…
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/external/llvm/test/Analysis/CFLAliasAnalysis/Steensgaard/ |
D | stratified-attrs-indexing.ll | 13 i32* %arg6, i32* %arg7, i32* %arg8, i32* %arg9, i32* %arg10,
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/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CFLAliasAnalysis/Steensgaard/ |
D | stratified-attrs-indexing.ll | 13 i32* %arg6, i32* %arg7, i32* %arg8, i32* %arg9, i32* %arg10,
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/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
D | 8bit.pnacl.ll | 522 …2 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) { 536 %trunc10 = trunc i32 %arg10 to i8
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/external/vixl/test/aarch64/ |
D | test-assembler-aarch64.cc | 27401 double arg10) { in runtime_call_two_arguments_on_stack() argument 27402 return arg9 - arg10; in runtime_call_two_arguments_on_stack()
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