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Searched refs:argw (Results 1 – 10 of 10) sorted by relevance

/external/pcre/dist2/src/sljit/
DsljitNativeARM_32.c1335 sljit_s32 arg, sljit_sw argw, sljit_s32 tmp_reg) in emit_op_mem() argument
1345 FAIL_IF(load_immediate(compiler, tmp_reg, argw & ~0xfff)); in emit_op_mem()
1346 argw &= 0xfff; in emit_op_mem()
1349 FAIL_IF(load_immediate(compiler, tmp_reg, argw & ~0xff)); in emit_op_mem()
1350 argw &= 0xff; in emit_op_mem()
1354 is_type1_transfer ? argw : TYPE2_TRANSFER_IMM(argw))); in emit_op_mem()
1360 argw &= 0x3; in emit_op_mem()
1362 if (argw != 0 && !is_type1_transfer) { in emit_op_mem()
1363 FAIL_IF(push_inst(compiler, ADD | RD(tmp_reg) | RN(arg) | RM(offset_reg) | (argw << 7))); in emit_op_mem()
1369 RM(offset_reg) | (is_type1_transfer ? (1 << 25) : 0) | (argw << 7))); in emit_op_mem()
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DsljitNativeARM_64.c812 sljit_s32 arg, sljit_sw argw, sljit_s32 tmp_reg) in emit_op_mem() argument
823 argw &= 0x3; in emit_op_mem()
825 if (argw == 0 || argw == shift) in emit_op_mem()
827 | RN(arg & REG_MASK) | RM(OFFS_REG(arg)) | (argw ? (1 << 12) : 0)); in emit_op_mem()
829 …FAIL_IF(push_inst(compiler, ADD | RD(tmp_reg) | RN(arg & REG_MASK) | RM(OFFS_REG(arg)) | (argw << … in emit_op_mem()
836 FAIL_IF(load_immediate(compiler, tmp_reg, argw & ~(0xfff << shift))); in emit_op_mem()
838 argw = (argw >> shift) & 0xfff; in emit_op_mem()
840 return push_inst(compiler, STRBI | type | RT(reg) | RN(tmp_reg) | (argw << 10)); in emit_op_mem()
843 if (argw >= 0 && (argw & ((1 << shift) - 1)) == 0) { in emit_op_mem()
844 if ((argw >> shift) <= 0xfff) { in emit_op_mem()
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DsljitNativeTILEGX_64.c1288 …t(struct sljit_compiler *compiler, sljit_s32 flags, sljit_s32 reg_ar, sljit_s32 arg, sljit_sw argw) in getput_arg_fast() argument
1293 && !(arg & OFFS_REG_MASK) && argw <= SIMM_16BIT_MAX && argw >= SIMM_16BIT_MIN) { in getput_arg_fast()
1298 FAIL_IF(ADDLI(ADDR_TMP_mapped, reg_map[arg & REG_MASK], argw)); in getput_arg_fast()
1314 static sljit_s32 can_cache(sljit_s32 arg, sljit_sw argw, sljit_s32 next_arg, sljit_sw next_argw) in can_cache() argument
1320 argw &= 0x3; in can_cache()
1322 if (argw && argw == next_argw in can_cache()
1329 if (((next_argw - argw) <= SIMM_16BIT_MAX in can_cache()
1330 && (next_argw - argw) >= SIMM_16BIT_MIN)) in can_cache()
1340 …ler *compiler, sljit_s32 flags, sljit_s32 reg_ar, sljit_s32 arg, sljit_sw argw, sljit_s32 next_arg… in getput_arg() argument
1358 argw &= 0x3; in getput_arg()
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DsljitNativeMIPS_common.c584 …(struct sljit_compiler *compiler, sljit_s32 flags, sljit_s32 reg_ar, sljit_s32 arg, sljit_sw argw);
755 …t(struct sljit_compiler *compiler, sljit_s32 flags, sljit_s32 reg_ar, sljit_s32 arg, sljit_sw argw) in getput_arg_fast() argument
759 if (!(arg & OFFS_REG_MASK) && argw <= SIMM_MAX && argw >= SIMM_MIN) { in getput_arg_fast()
764 …| TA(reg_ar) | IMM(argw), ((flags & MEM_MASK) <= GPR_REG && (flags & LOAD_DATA)) ? reg_ar : MOVABL… in getput_arg_fast()
773 static sljit_s32 can_cache(sljit_s32 arg, sljit_sw argw, sljit_s32 next_arg, sljit_sw next_argw) in can_cache() argument
779 argw &= 0x3; in can_cache()
781 …if (argw && argw == next_argw && (arg == next_arg || (arg & OFFS_REG_MASK) == (next_arg & OFFS_REG… in can_cache()
787 if (((next_argw - argw) <= SIMM_MAX && (next_argw - argw) >= SIMM_MIN)) in can_cache()
796 …ler *compiler, sljit_s32 flags, sljit_s32 reg_ar, sljit_s32 arg, sljit_sw argw, sljit_s32 next_arg… in getput_arg() argument
817 argw &= 0x3; in getput_arg()
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DsljitNativeARM_T2_32.c850 #define OFFSET_CHECK(imm, shift) (!(argw & ~(imm << shift)))
944 sljit_s32 arg, sljit_sw argw, sljit_s32 tmp_reg) in emit_op_mem() argument
954 tmp = get_imm(argw & ~0xfff); in emit_op_mem()
957 …return push_inst32(compiler, sljit_mem32[flags] | MEM_IMM12 | RT4(reg) | RN4(tmp_reg) | (argw & 0x… in emit_op_mem()
960 FAIL_IF(load_immediate(compiler, tmp_reg, argw)); in emit_op_mem()
967 argw &= 0x3; in emit_op_mem()
971 if (!argw && IS_3_LO_REGS(reg, arg, other_r)) in emit_op_mem()
973 …return push_inst32(compiler, sljit_mem32[flags] | RT4(reg) | RN4(arg) | RM4(other_r) | (argw << 4)… in emit_op_mem()
976 if (argw > 0xfff) { in emit_op_mem()
977 tmp = get_imm(argw & ~0xfff); in emit_op_mem()
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DsljitNativeSPARC_common.c560 …fast(struct sljit_compiler *compiler, sljit_s32 flags, sljit_s32 reg, sljit_s32 arg, sljit_sw argw) in getput_arg_fast() argument
564 if ((!(arg & OFFS_REG_MASK) && argw <= SIMM_MAX && argw >= SIMM_MIN) in getput_arg_fast()
565 || ((arg & OFFS_REG_MASK) && (argw & 0x3) == 0)) { in getput_arg_fast()
571 | S1(arg & REG_MASK) | ((arg & OFFS_REG_MASK) ? S2(OFFS_REG(arg)) : IMM(argw)), in getput_arg_fast()
581 static sljit_s32 can_cache(sljit_s32 arg, sljit_sw argw, sljit_s32 next_arg, sljit_sw next_argw) in can_cache() argument
587 argw &= 0x3; in can_cache()
588 SLJIT_ASSERT(argw); in can_cache()
590 if ((arg & OFFS_REG_MASK) == (next_arg & OFFS_REG_MASK) && argw == next_argw) in can_cache()
595 if (((next_argw - argw) <= SIMM_MAX && (next_argw - argw) >= SIMM_MIN)) in can_cache()
601 …mpiler *compiler, sljit_s32 flags, sljit_s32 reg, sljit_s32 arg, sljit_sw argw, sljit_s32 next_arg… in getput_arg() argument
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DsljitNativePPC_common.c896 sljit_s32 arg, sljit_sw argw, sljit_s32 tmp_reg) in emit_op_mem() argument
907 argw &= 0x3; in emit_op_mem()
910 if (argw != 0) { in emit_op_mem()
912 …FAIL_IF(push_inst(compiler, RLWINM | S(OFFS_REG(arg)) | A(tmp_reg) | (argw << 11) | ((31 - argw) <… in emit_op_mem()
914 FAIL_IF(push_inst(compiler, RLDI(tmp_reg, OFFS_REG(arg), argw, 63 - argw, 1))); in emit_op_mem()
932 if ((inst & INT_ALIGNED) && (argw & 0x3) != 0) { in emit_op_mem()
933 FAIL_IF(load_immediate(compiler, tmp_reg, argw)); in emit_op_mem()
940 if (argw <= SIMM_MAX && argw >= SIMM_MIN) in emit_op_mem()
941 return push_inst(compiler, INST_CODE_AND_DST(inst, inp_flags, reg) | A(arg) | IMM(argw)); in emit_op_mem()
944 if (argw <= 0x7fff7fffl && argw >= -0x80000000l) { in emit_op_mem()
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DsljitNativeX86_common.c1377 #define BINARY_IMM(op_imm, op_mr, immw, arg, argw) \ argument
1379 inst = emit_x86_instruction(compiler, 1 | EX86_BIN_INS, SLJIT_IMM, immw, arg, argw); \
1385 inst = emit_x86_instruction(compiler, 1, (arg == TMP_REG1) ? TMP_REG2 : TMP_REG1, 0, arg, argw); \
1395 #define BINARY_IMM(op_imm, op_mr, immw, arg, argw) \ argument
1396 inst = emit_x86_instruction(compiler, 1 | EX86_BIN_INS, SLJIT_IMM, immw, arg, argw); \
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dicmp-range.ll49 define i1 @test_nonzero6(i8* %argw) {
52 %val = load i8, i8* %argw, !range !3
/external/llvm/test/Transforms/InstCombine/
Dicmp-range.ll49 define i1 @test_nonzero6(i8* %argw) {
52 %val = load i8, i8* %argw, !range !3