| /external/mesa3d/src/amd/addrlib/inc/chip/r800/ |
| D | si_gb_reg.h | 106 unsigned int array_mode : 4; member
138 unsigned int array_mode : 4; member
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | r600_texture.c | 223 enum radeon_surf_mode array_mode, in r600_init_surface() argument
253 array_mode == RADEON_SURF_MODE_2D)) { in r600_init_surface()
296 array_mode, surface); in r600_init_surface()
353 enum radeon_surf_mode *array_mode, in r600_surface_import_metadata() argument
358 *array_mode = RADEON_SURF_MODE_2D; in r600_surface_import_metadata()
360 *array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED; in r600_surface_import_metadata()
375 *array_mode = RADEON_SURF_MODE_2D; in r600_surface_import_metadata()
377 *array_mode = RADEON_SURF_MODE_1D; in r600_surface_import_metadata()
379 *array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED; in r600_surface_import_metadata()
1468 enum radeon_surf_mode array_mode; in r600_texture_from_handle() local
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| /external/mesa3d/src/gallium/drivers/nouveau/nv50/ |
| D | nv50_state_validate.c | 26 uint32_t array_size = 0xffff, array_mode = 0; in nv50_validate_fb() local
52 array_mode = NV50_3D_RT_ARRAY_MODE_MODE_3D; /* 1 << 16 */ in nv50_validate_fb()
55 assert(mt->layout_3d || !array_mode || array_size == 1); in nv50_validate_fb()
70 PUSH_DATA (push, array_mode | array_size); in nv50_validate_fb()
71 nv50->rt_array_mode = array_mode | array_size; in nv50_validate_fb()
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_texture.c | 199 enum radeon_surf_mode array_mode, in r600_init_surface() argument
249 array_mode, surface); in r600_init_surface()
297 enum radeon_surf_mode *array_mode, in r600_surface_import_metadata() argument
308 *array_mode = RADEON_SURF_MODE_2D; in r600_surface_import_metadata()
310 *array_mode = RADEON_SURF_MODE_1D; in r600_surface_import_metadata()
312 *array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED; in r600_surface_import_metadata()
1103 enum radeon_surf_mode array_mode; in r600_texture_from_handle() local
1121 &array_mode, &is_scanout); in r600_texture_from_handle()
1123 r = r600_init_surface(rscreen, &surface, templ, array_mode, stride, in r600_texture_from_handle()
1886 enum radeon_surf_mode array_mode; in r600_texture_from_memobj() local
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| D | r600_state.c | 671 unsigned char swizzle[4], array_mode = 0; in r600_create_sampler_view_custom() local
740 array_mode = V_038000_ARRAY_LINEAR_ALIGNED; in r600_create_sampler_view_custom()
743 array_mode = V_038000_ARRAY_1D_TILED_THIN1; in r600_create_sampler_view_custom()
746 array_mode = V_038000_ARRAY_2D_TILED_THIN1; in r600_create_sampler_view_custom()
752 S_038000_TILE_MODE(array_mode) | in r600_create_sampler_view_custom()
1042 unsigned level, pitch, slice, format, offset, array_mode; in r600_init_depth_surface() local
1053 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; in r600_init_depth_surface()
1058 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; in r600_init_depth_surface()
1065 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format); in r600_init_depth_surface()
2855 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size; in r600_dma_copy_tile() local
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| D | evergreen_state.c | 717 unsigned char array_mode = 0, non_disp_tiling = 0; in evergreen_fill_tex_resource_words() local
788 array_mode = V_028C70_ARRAY_LINEAR_ALIGNED; in evergreen_fill_tex_resource_words()
791 array_mode = V_028C70_ARRAY_2D_TILED_THIN1; in evergreen_fill_tex_resource_words()
794 array_mode = V_028C70_ARRAY_1D_TILED_THIN1; in evergreen_fill_tex_resource_words()
837 S_030004_ARRAY_MODE(array_mode)); in evergreen_fill_tex_resource_words()
1344 unsigned format, array_mode; in evergreen_init_depth_surface() local
1356 array_mode = V_028C70_ARRAY_2D_TILED_THIN1; in evergreen_init_depth_surface()
1361 array_mode = V_028C70_ARRAY_1D_TILED_THIN1; in evergreen_init_depth_surface()
1375 surf->db_z_info = S_028040_ARRAY_MODE(array_mode) | in evergreen_init_depth_surface()
3697 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size; in evergreen_dma_copy_tile() local
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_dma.c | 145 unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size; in si_dma_copy_tile() local
167 array_mode = G_009910_ARRAY_MODE(tile_mode); in si_dma_copy_tile()
203 radeon_emit(cs, (detile << 31) | (array_mode << 27) | in si_dma_copy_tile()
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_image.c | 72 unsigned array_mode = radv_choose_tiling(device, create_info); in radv_init_surface() local
88 surface->flags = RADEON_SURF_SET(array_mode, MODE); in radv_init_surface()
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| /external/mesa3d/src/amd/addrlib/r800/ |
| D | ciaddrlib.cpp | 1598 UINT_32 regArrayMode = gbTileMode.f.array_mode; in ReadGbTileMode()
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| D | siaddrlib.cpp | 3056 UINT_32 regArrayMode = gbTileMode.f.array_mode; in ReadGbTileMode()
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