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Searched refs:assm (Results 1 – 14 of 14) sorted by relevance

/external/v8/src/wasm/baseline/ia32/
Dliftoff-assembler-ia32.h51 inline void Load(LiftoffAssembler* assm, LiftoffRegister dst, Register base, in Load() argument
56 assm->mov(dst.gp(), src); in Load()
59 assm->mov(dst.low_gp(), src); in Load()
60 assm->mov(dst.high_gp(), Operand(base, offset + 4)); in Load()
63 assm->movss(dst.fp(), src); in Load()
66 assm->movsd(dst.fp(), src); in Load()
73 inline void Store(LiftoffAssembler* assm, Register base, int32_t offset, in Store() argument
78 assm->mov(dst, src.gp()); in Store()
81 assm->mov(dst, src.low_gp()); in Store()
82 assm->mov(Operand(base, offset + 4), src.high_gp()); in Store()
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/external/v8/src/wasm/baseline/x64/
Dliftoff-assembler-x64.h51 inline Operand GetMemOp(LiftoffAssembler* assm, Register addr, Register offset, in GetMemOp() argument
59 assm->movl(scratch, Immediate(offset_imm)); in GetMemOp()
61 assm->addq(scratch, offset); in GetMemOp()
66 inline void Load(LiftoffAssembler* assm, LiftoffRegister dst, Operand src, in Load() argument
70 assm->movl(dst.gp(), src); in Load()
73 assm->movq(dst.gp(), src); in Load()
76 assm->Movss(dst.fp(), src); in Load()
79 assm->Movsd(dst.fp(), src); in Load()
86 inline void Store(LiftoffAssembler* assm, Operand dst, LiftoffRegister src, in Store() argument
90 assm->movl(dst, src.gp()); in Store()
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/external/v8/src/wasm/baseline/mips/
Dliftoff-assembler-mips.h36 inline void Load(LiftoffAssembler* assm, LiftoffRegister dst, Register base, in Load() argument
41 assm->lw(dst.gp(), src); in Load()
44 assm->lw(dst.low_gp(), src); in Load()
45 assm->lw(dst.high_gp(), MemOperand(base, offset + 4)); in Load()
48 assm->lwc1(dst.fp(), src); in Load()
51 assm->Ldc1(dst.fp(), src); in Load()
58 inline void Store(LiftoffAssembler* assm, Register base, int32_t offset, in Store() argument
63 assm->Usw(src.gp(), dst); in Store()
66 assm->Usw(src.low_gp(), dst); in Store()
67 assm->Usw(src.high_gp(), MemOperand(base, offset + 4)); in Store()
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/external/v8/src/
Dassembler.cc234 void ConstantPoolBuilder::EmitSharedEntries(Assembler* assm, in EmitSharedEntries() argument
244 int offset = assm->pc_offset() - base; in EmitSharedEntries()
247 assm->dp(shared_it->value()); in EmitSharedEntries()
249 assm->dq(shared_it->value64()); in EmitSharedEntries()
254 assm->PatchConstantPoolAccessInstruction(shared_it->position(), offset, in EmitSharedEntries()
259 void ConstantPoolBuilder::EmitGroup(Assembler* assm, in EmitGroup() argument
274 EmitSharedEntries(assm, type); in EmitGroup()
295 offset = assm->pc_offset() - base; in EmitGroup()
298 assm->dp(it->value()); in EmitGroup()
300 assm->dq(it->value64()); in EmitGroup()
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Dassembler.h531 int Emit(Assembler* assm);
542 void EmitSharedEntries(Assembler* assm, ConstantPoolEntry::Type type);
543 void EmitGroup(Assembler* assm, ConstantPoolEntry::Access access,
/external/v8/src/wasm/baseline/mips64/
Dliftoff-assembler-mips64.h31 inline void Load(LiftoffAssembler* assm, LiftoffRegister dst, MemOperand src, in Load() argument
35 assm->lw(dst.gp(), src); in Load()
38 assm->ld(dst.gp(), src); in Load()
41 assm->lwc1(dst.fp(), src); in Load()
44 assm->Ldc1(dst.fp(), src); in Load()
51 inline void Store(LiftoffAssembler* assm, Register base, int32_t offset, in Store() argument
56 assm->Usw(src.gp(), dst); in Store()
59 assm->Usd(src.gp(), dst); in Store()
62 assm->Uswc1(src.fp(), dst, t8); in Store()
65 assm->Usdc1(src.fp(), dst, t8); in Store()
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/external/v8/src/wasm/baseline/
Dliftoff-assembler.h617 void EmitI64IndependentHalfOperation(LiftoffAssembler* assm, in EmitI64IndependentHalfOperation() argument
623 (assm->*op)(dst.low_gp(), lhs.low_gp(), rhs.low_gp()); in EmitI64IndependentHalfOperation()
624 (assm->*op)(dst.high_gp(), lhs.high_gp(), rhs.high_gp()); in EmitI64IndependentHalfOperation()
630 (assm->*op)(dst.high_gp(), lhs.high_gp(), rhs.high_gp()); in EmitI64IndependentHalfOperation()
631 (assm->*op)(dst.low_gp(), lhs.low_gp(), rhs.low_gp()); in EmitI64IndependentHalfOperation()
636 assm->GetUnusedRegister(kGpReg, LiftoffRegList::ForRegs(lhs, rhs)).gp(); in EmitI64IndependentHalfOperation()
637 (assm->*op)(tmp, lhs.low_gp(), rhs.low_gp()); in EmitI64IndependentHalfOperation()
638 (assm->*op)(dst.high_gp(), lhs.high_gp(), rhs.high_gp()); in EmitI64IndependentHalfOperation()
639 assm->Move(dst.low_gp(), tmp, kWasmI32); in EmitI64IndependentHalfOperation()
/external/vixl/test/aarch32/
Dtest-assembler-aarch32.cc3103 void CheckInstructionSetA32(const T& assm) { in CheckInstructionSetA32() argument
3104 VIXL_CHECK(assm.IsUsingA32()); in CheckInstructionSetA32()
3105 VIXL_CHECK(!assm.IsUsingT32()); in CheckInstructionSetA32()
3106 VIXL_CHECK(assm.GetInstructionSetInUse() == A32); in CheckInstructionSetA32()
3111 void CheckInstructionSetT32(const T& assm) { in CheckInstructionSetT32() argument
3112 VIXL_CHECK(assm.IsUsingT32()); in CheckInstructionSetT32()
3113 VIXL_CHECK(!assm.IsUsingA32()); in CheckInstructionSetT32()
3114 VIXL_CHECK(assm.GetInstructionSetInUse() == T32); in CheckInstructionSetT32()
3170 Assembler assm; in TEST_NOASM() local
3171 CheckInstructionSetA32(assm); in TEST_NOASM()
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/external/v8/src/x64/
Dmacro-assembler-x64.h125 Assembler* assm; member
132 CpuFeatureScope scope(assm, AVX); in emit()
133 (assm->*avx)(dst, dst, args...); in emit()
135 (assm->*no_avx)(dst, args...); in emit()
144 CpuFeatureScope scope(assm, AVX); in emit()
145 (assm->*avx)(dst, args...); in emit()
147 (assm->*no_avx)(dst, args...); in emit()
Dassembler-x64.h424 explicit ConstPool(Assembler* assm) : assm_(assm) {} in ConstPool() argument
/external/v8/src/arm64/
Dutils-arm64.cc13 #define __ assm->
Dassembler-arm64.h829 explicit ConstPool(Assembler* assm) : assm_(assm), first_use_(-1) {} in ConstPool() argument
/external/vixl/test/aarch64/
Dtest-utils-aarch64.h83 void Dump(MacroAssembler* assm);
/external/v8/src/wasm/baseline/arm64/
Dliftoff-assembler-arm64.h99 inline MemOperand GetMemOp(LiftoffAssembler* assm, in GetMemOp() argument
109 assm->Add(tmp, offset.W(), offset_imm); in GetMemOp()