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/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td231 def : TLBI<"IPAS2E1IS", 0b01, 0b100, 0b1000, 0b0000, 0b001>;
232 def : TLBI<"IPAS2LE1IS", 0b01, 0b100, 0b1000, 0b0000, 0b101>;
312 def : ROSysReg<"MDCCSR_EL0", 0b10, 0b011, 0b0000, 0b0001, 0b000>;
313 def : ROSysReg<"DBGDTRRX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>;
314 def : ROSysReg<"MDRAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b000>;
319 def : ROSysReg<"MIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b000>;
320 def : ROSysReg<"CCSIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b000>;
321 def : ROSysReg<"CLIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b001>;
322 def : ROSysReg<"CTR_EL0", 0b11, 0b011, 0b0000, 0b0000, 0b001>;
323 def : ROSysReg<"MPIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b101>;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td336 def : TLBI<"IPAS2E1IS", 0b100, 0b1000, 0b0000, 0b001>;
337 def : TLBI<"IPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b101>;
403 def : TLBI<"RIPAS2E1IS", 0b100, 0b1000, 0b0000, 0b010>;
404 def : TLBI<"RIPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b110>;
470 def : ROSysReg<"MDCCSR_EL0", 0b10, 0b011, 0b0000, 0b0001, 0b000>;
471 def : ROSysReg<"DBGDTRRX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>;
472 def : ROSysReg<"MDRAR_EL1", 0b10, 0b000, 0b0001, 0b0000, 0b000>;
477 def : ROSysReg<"MIDR_EL1", 0b11, 0b000, 0b0000, 0b0000, 0b000>;
478 def : ROSysReg<"CCSIDR_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b000>;
479 def : ROSysReg<"CCSIDR2_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b010> {
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DAArch64SVEInstrInfo.td128 defm FADD_ZPmZ : sve_fp_2op_p_zds<0b0000, "fadd">;
250 def AND_PPzPP : sve_int_pred_log<0b0000, "and">;
279 defm LD1B_IMM : sve_mem_cld_si<0b0000, "ld1b", Z_b, ZPR8>;
325 defm LD1B : sve_mem_cld_ss<0b0000, "ld1b", Z_b, ZPR8, GPR64NoXZRshifted8>;
343 defm LDNF1B_IMM : sve_mem_cldnf_si<0b0000, "ldnf1b", Z_b, ZPR8>;
361 defm LDFF1B : sve_mem_cldff_ss<0b0000, "ldff1b", Z_b, ZPR8, GPR64shifted8>;
408 …defm GLD1SB_S : sve_mem_32b_gld_vs_32_unscaled<0b0000, "ld1sb", ZPR32ExtSXTW8Only, ZPR32ExtUXT…
430 defm GLD1SB_S : sve_mem_32b_gld_vi_32_ptrs<0b0000, "ld1sb", imm0_31>;
443 defm GLD1SB_D : sve_mem_64b_gld_vi_64_ptrs<0b0000, "ld1sb", imm0_31>;
460 defm GLD1SB_D : sve_mem_64b_gld_vs2_64_unscaled<0b0000, "ld1sb">;
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/external/vboot_reference/tests/futility/
Ddata_fmap2_expect_hhH.txt22 001b0000 001af000 fffff000 // gap in WP_RO
23 RO_VPD 001a0000 001b0000 00010000
26 GBB 000b0000 0019f000 000ef000
27 RO_FRID 000aff00 000b0000 00000100
Ddata_fmap2_expect_hh.txt20 RO_VPD 001a0000 001b0000 00010000
22 GBB 000b0000 0019f000 000ef000
23 RO_FRID 000aff00 000b0000 00000100
/external/llvm/lib/Target/Hexagon/
DHexagonInstrEnc.td249 let Inst{31-16} = { 0b00011110, src1{1-0}, 0b0000, opc{4-3} };
311 class V6_vL32b_ai_enc : Enc_COPROC_VMEM_vL32_b_ai<0b0000>;
330 class V6_vL32b_ai_128B_enc : Enc_COPROC_VMEM_vL32_b_ai_128B<0b0000>;
360 class V6_vS32b_ai_enc : Enc_COPROC_VMEM_vS32_b_ai_64B<0b0000>;
364 class V6_vS32b_ai_128B_enc : Enc_COPROC_VMEM_vS32_b_ai_128B<0b0000>;
454 class V6_vS32b_new_pred_ai_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai<0b0000>;
471 class V6_vS32b_new_pred_ai_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai_128B<0b0000>;
489 class V6_vL32b_pi_enc : Enc_COPROC_VMEM_vL32_b_pi<0b0000>;
508 class V6_vL32b_pi_128B_enc : Enc_COPROC_VMEM_vL32_b_pi_128B<0b0000>;
530 class V6_vS32b_pi_enc : Enc_COPROC_VMEM_vS32_b_pi<0b0000>;
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/external/u-boot/arch/arm/dts/
Dtegra210-e2220-1170.dts16 mmc1 = "/sdhci@700b0000";
24 sdhci@700b0000 {
Dtegra210-p2371-0000.dts16 mmc1 = "/sdhci@700b0000";
24 sdhci@700b0000 {
Dtegra210-p2371-2180.dts16 mmc1 = "/sdhci@700b0000";
74 sdhci@700b0000 {
Dtegra210-p2571.dts21 mmc1 = "/sdhci@700b0000";
77 sdhci@700b0000 {
Ddragonboard410c.dts33 stdout-path = "/soc/serial@78b0000";
60 serial@78b0000 {
Dexynos54xx.dtsi36 spi4 = "/spi@131b0000";
180 dp: dp@145b0000 {
Ddragonboard820c-uboot.dtsi16 serial@75b0000 {
Dexynos5.dtsi114 spi_4: spi@131b0000 {
147 dp: dp@145b0000 {
Ddragonboard410c-uboot.dtsi24 serial@78b0000 {
Duniphier-support-card.dtsi26 serialsc: uart@b0000 {
/external/u-boot/doc/device-tree-bindings/video/
Dexynos-dp.txt48 dp@145b0000 {
56 dp@145b0000 {
/external/u-boot/board/buffalo/lsxl/
Dkwbimage-lsxhl.cfg179 # bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
180 # bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
183 # bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
195 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
Dkwbimage-lschl.cfg179 # bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
180 # bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
195 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-3
/external/u-boot/board/d-link/dns325/
Dkwbimage.cfg161 # bit3-0: 0b0000, (read) M_ODT[0] is not asserted during read from DRAM
162 # bit7-4: 0b0000, (read) M_ODT[1] is not asserted during read from DRAM
165 # bit23-20: 0b0000, (write) M_ODT[1] is not asserted during write to DRAM
175 # bit7-4: 0b0000, internal ODT is not asserted during write to DRAM bank 0-4
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dinvalid-LDC-form-arm.txt9 # The bytes have 0b0000 for P,U,D,W; from A8.6.51, it is undefined.
Dinvalid-MOVr-arm.txt8 # To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b110…
Dinvalid-MOVs-arm.txt8 # To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1…
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrVFP.td308 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
313 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
327 let Inst{3-0} = 0b0000;
335 let Inst{3-0} = 0b0000;
348 let Inst{3-0} = 0b0000;
356 let Inst{3-0} = 0b0000;
451 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
455 def VMOVS : ASuI<0b11101, 0b11, 0b0000, 0b01, 0,
478 let Inst{3-0} = 0b0000;
499 let Inst{3-0} = 0b0000;
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/external/llvm/lib/Target/ARM/
DARMInstrVFP.td546 def VABSD : ADuI<0b11101, 0b11, 0b0000, 0b11, 0,
551 def VABSS : ASuIn<0b11101, 0b11, 0b0000, 0b11, 0,
560 def VABSH : AHuI<0b11101, 0b11, 0b0000, 0b11, 0,
570 let Inst{3-0} = 0b0000;
578 let Inst{3-0} = 0b0000;
590 let Inst{3-0} = 0b0000;
599 let Inst{3-0} = 0b0000;
607 let Inst{3-0} = 0b0000;
619 let Inst{3-0} = 0b0000;
962 def VMOVD : ADuI<0b11101, 0b11, 0b0000, 0b01, 0,
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